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半导体行业从未遇到过像现在这样由人工智能需求激增带来的巨大冲击。
There's never been as big a shock to the semiconductor industry as the current surge in demand from AI.
人工智能正在推动巨大的计算需求。
AI is driving incredible computing demand.
轻松超出我们最大产能的40%到50%，这是我从未见过的。
Easily 40% to 50% above our maximum capacity, which I've never seen before.
人工智能的进步是由计算能力的指数级增长推动的。
Progress in AI has been driven by exponentially increasing compute.
为了维持这种进步，像英特尔这样的代工厂需要制造更多的尖端计算产品，既要生产更多的芯片，也要提升每颗芯片的性能。
To sustain that progress, foundries like Intel will need to manufacture far more leading-edge compute, both by producing more chips and by improving what each chip can do.
但这些芯片的生产受制于英特尔从供应商那里购买的设备，最著名的就是ASML的EUV光刻机。
But the production of these chips is bottlenecked by tools that Intel buys from their suppliers, most famously ASML's EUV machines.
如果没有这些设备，他们就没法在这里制造芯片。
If they don't have the equipment, they can't make the chips here.
我花了两天时间参观英特尔的晶圆厂，为采访其领导层做准备。
I spent two days touring Intel's fabs to prepare for these interviews with its leadership.
我想了解制造世界上最先进的芯片需要什么，以及硬件如何塑造AI的未来。
I wanted to understand what it takes to manufacture the world's most advanced chips and how hardware is shaping the future of AI.
好的，我身边的是Chris Auth，他负责所有目前正在量产中的工艺的开发。
Okay, I'm joined by Chris Auth, who leads development of all the processes that are currently under manufacturing.
我想更具体地了解新工艺的开发实际上是如何进行的。
The thing I want to understand in more concrete detail is how the development of a new process actually happens.
所以如果14A将在两三年后推出，从现在到那时会发生什么？
So if 14A is going to come out in three years or two years from now, what is happening from now till then?
我希望你能尽可能详细地给我讲解，从良率如何提升，你们看哪些遥测数据，所有这些。
And I want you to walk me through as much detail as you can, everything from the level of how is the yield improving, what kind of telemetry do you guys look at?
你们会做哪些实验？
What kind of experiments do you guys run?
我想尽可能具体地了解未来两年会发生什么。
I want to understand what is going to happen over the next two years as concretely as possible.
如果我们谈论14A，14A实际上在这个阶段已经开发了三年多了。
And if we talk about 14A, 14A has actually been in development for about three-plus years at this stage.
所以其实已经做了不少前期工作，才让它达到现在的状态。
And so quite a bit of pre-work has been done to get it to the stage that it's at right now.
而现在，我们非常接近最终确定这个工艺的阶段了。
And right now, we're getting very close to where we're finalizing the process.
我们正在确定生产所用的设备组合，同时也在对每个工艺步骤进行精细调整。
We're finalizing the tool sets that it will be manufactured on, and we're working on the fine-tuning of each of the process steps.
工厂里大概有两千个步骤要走，每一步都需要非常精细的操作，确保它调整到位，能够投入量产，每周在这个工艺上跑几千片晶圆，而且每次都能保持一致性。
There's about 2,000 steps in the factory that you have to go do, and you need to do really intricate work at each one of those to make sure it's fine-tuned, it can go into manufacturing, it can run thousands of wafers a week on this process, and it can be repeatable every single time.
现在，你们可能有一个良率。
Right now, you might have a certain yield.
跟我说说这个良率是怎么逐月提升的。
Walk me through how that increases month over month.
所以有一条产线在跑14A。
So there's a line running at 14A.
对。
Yep.
从现在到下个月，会发生什么导致良率变化？
What happens from now till next month that will result in the yield changing?
你怎么找出缺陷在哪里？
How do you identify where the defects are?
你怎么修复它？
How do you fix that?
我们有一个持续的过程来识别缺陷，主要有两种方式。
So there's a constant process that we go through in identifying defects, and there's two main ways that we'll identify defects.
一种是在线计量检测。
One is we have in-line metrology.
我们有工具会检查晶圆，然后说：“啊，这里有个缺陷。
So we have tools that will look at the wafers and say, "Ah, there's a defect there.
那里有个缺陷。
There's a defect there.
那里也有个缺陷。”
There's a defect there."
另外，在生产线末端，要么做电性测试，要么做分选，看看哪里出了问题，找出失效点，然后对这些失效点进行分析。
And then also at end of line, either electrical test or we sort and see where the fails are, and we will identify failures, and then we will get analysis on those failures.
我们会做截面分析。
We'll cross-section it.
你昨天在透射电镜实验室，看到了怎么做截面。
You were in the TEM lab yesterday, and you saw how you can get cross-sections.
你会得到缺陷的截面，然后就能判断，哦，这个缺陷在两层之间，所以肯定来自流程的某个环节。
You'll get a cross-section of a defect, and from that, you'll be able to say, "Oh, that defect is between these layers, so it must have come from this section of the flow.
哦，那个环节我们有在线检测，已经发现了缺陷。
Oh, we have in-line metrology in that section, which has identified defects.
那些就是我们需要重点处理的缺陷。
Those are the defects we need to go after."
我觉得我们学到的经验是，在一个节点上不要做太多创新，因为创新越多，复杂度就越高。
I think what we've learned is that you don't want to do too much innovation in one node because the more innovation that you did, the more complex it becomes.
虽然最终能搞定，但你必须赶上进度，而这个进度是客户最终要求的。
And while you'll be able to get that to work, you need to hit a certain schedule, and that's the schedule that your customer ultimately wants.
所以，拥有一个可预测的时间表是非常关键的。
And so having that predictable schedule is a key piece.
因此，你必须弄清楚在满足客户要求的时间范围内，你能投入多少创新。
So you've got to figure out how much innovation you can put in in order to meet the customer's requirements in the timeline that they needed.
英特尔深刻体会到了这种权衡的代价，其10纳米工艺节点原定于2016年推出，但直到2018年才开始量产。
Intel learned how costly that trade-off can be with delays to its 10 nanometer node, whose original target launch date was 2016, but which didn't begin manufacturing until 2018.
通常，英特尔一直是摩尔定律的守护者，每两年更新一次制造工艺。
Usually, Intel has been the keeper of Moore's law, a new cadence of manufacturing every two years.
但他们最近的一系列产品却推迟了将近四年。
But their last set of products slipped almost four years.
英特尔今天遭遇了四个月来最糟糕的一天。
Intel today having its worst day in four months.
股价目前下跌超过15%。
The stock now down more than 15%.
我还想指出，台积电因英特尔的坏消息而上涨了13%。
I also want to point out Taiwan Semiconductor, up 13% off of Intel's bad news.
跟我说说，你觉得英特尔从10纳米工艺中学到了什么教训？
Walk me through what lessons you think Intel has learned from 10 nanometer.
10纳米就是一个很好的例子，说明我们当时的目标定得太激进了。
10 nanometer was a good example of where we had very aggressive targets.
我们当时在做所谓的超缩放，也就是说我们的缩放速度比以往任何时候都要快得多。
We were doing what was called hyperscaling at the time, so we were scaling much faster than what had been historically done.
为了做到这一点，我们想出了各种创新的办法，试图在没有新工具的情况下实现目标，因为工具还没准备好。
In order to do that, we came up with all sorts of innovative ideas and how we could achieve that without new tools because the tools weren't ready.
这样一来，就给工艺本身和工程师们带来了巨大的压力。
And so that put a lot of burden on the process and a lot of burden on the engineers in order to do that.
不过说到底，10纳米技术本身是很棒的。
Now, at the end of the day, 10 nanometers are great technology.
它的良率是世界级的，性能是世界级的，成本也是世界级的。
It has world-class yield, it has world-class performance, and it has world-class cost.
但我们花的时间比我们预期的要长。
But it took us longer to do that than what we would've liked.
所以我们试着把那个教训带到未来的技术节点上，说：‘嘿，我们需要限制投入的创新量，确保能按时完成。’
And so we've tried to take that learning into future technology nodes and say, "Hey, we need to limit the amount of innovation we put in there to make sure that we keep it on schedule."
你觉得哪项主要技术本该留到未来版本再用？
What do you think was the main technology that should've been saved for a future version?
EUV可能是最大的问题。
EUV was probably the big thing.
当我们开始定义10纳米时，结论是EUV还没准备好。
When we started to define 10 nanometer, what the conclusion was, EUV was not ready.
EUV是极紫外光刻技术。
EUV is extreme ultraviolet lithography.
它用13.5纳米波长的光来打印芯片图案，这比芯片制造商之前依赖的工具发出的光波长短约14倍。
It prints chip patterns with light at a wavelength of 13.5 nanometers, about 14 times shorter than that emitted by previous tools that chip makers had relied on.
波长越短，单次曝光能打印的细节就越精细。
The shorter the wavelength, the finer the features that a single exposure can print.
但英特尔认为这项技术当时来不及准备好。
But Intel decided this technology wasn't going to be ready in time.
台积电更早地转向了EUV。
TSMC transitioned to EUV much sooner.
它在2019年将EUV投入量产，并在2020年进一步扩大到了5纳米节点。
It put EUV into volume manufacturing in 2019 and ramped it up further on its 5 nanometer node in 2020.
英特尔的首个EUV工艺直到2023年才用于产品，所以台积电在这些机器上多积累了大约四年的经验。
Intel's first EUV process did not reach products until 2023, so TSMC had about four more years of experience with these machines.
所以昨天我们在研究实验室，提前看了一下——
So yesterday, we were at the research lab, and we were getting a preview of-
……
...
二维材料、CFET和钌互连，我很好奇你们是如何决定这些技术是否足够成熟，可以用于下一个节点的。
2D materials and CFET and ruthenium interconnects, and I'm curious about how you decide whether that technology is mature enough for the next node.
10纳米节点还带来了一点，就是我们开始定义一套成熟度指标。
One thing that did also come out of 10 nanometer is we started to define a set of maturity metrics.
我们把这些成熟度指标用在一个叫做阶段门的过程中，就是说，从路径探索进入开发阶段，我们需要达到这些标准，包括良率标准、缺陷标准和性能标准。
And so we use those maturity metrics in a process, which we call phase gate, where we would say, to go from pathfinding into development, these are the criteria that we need to go hit, and there's yield criteria, defect criteria, performance criteria.
我们必须达到这些标准才能进入下一阶段，如果有哪项没达标，那就错过了机会，这项技术就会被搁置，我们会专注于那些已经准备好、可以投入生产的项目，因为关键之一就是要按时完成。
And we need to hit those in order to move to the next set of the flow, and if there's something that doesn't make that, then it misses that And it goes on to the next technology, and we focus on the items that are ready and we can run and put into a process, because one of the key things is staying on schedule.
按时完成很难，部分原因是新的晶体管设计需要几十年的时间才能成熟。
Staying on schedule is hard, partly because new transistor designs take decades to mature.
现代芯片晶体管是从1960年展示的平面MOS晶体管演变而来的。
Modern chip transistors evolved from the planar MOS transistor, demonstrated in 1960.
自那以后，晶体管的发展就是从二维走向三维的过程。
The history of transistors since has been the progression from two dimensions into three.
克里斯接下来描述的每一项发展，从FinFET到全环绕栅极，都是这个进程中的一步。
Each development that Chris goes on to describe, from FinFET to gate-all-around, is a step in that progression.
所以先来看一个基本的晶体管以及它的各个部分是如何随时间变化的，会很有帮助。
So it'll help to first look at a basic transistor and how its parts have changed over time.
晶体管基本上就是一个开关。
A transistor is basically a switch.
当它打开时，电流可以在它的两端之间流动，这两端分别叫做源极和漏极。
When it's turned on, it allows current to flow between its two ends, which are called the source and the drain.
在硅片上方，源极和漏极之间，有一个叫做栅极的部件。
A piece called a gate sits on top of the silicon between the source and the drain.
给栅极加上正电压，开关就打开了，因为正电压会把硅片下面带负电的电子往上吸，吸向栅极。
Applying a positive voltage to the gate turns the switch on, because the positive voltage pulls negatively charged electrons in the silicon beneath up towards the gate.
不过，有一层很薄的绝缘层挡着，电子到不了栅极，它们就聚集在绝缘层下面，形成一条从源极到漏极的薄薄的导电通道。
However, a thin layer of insulation stops them from actually reaching the gate, so the electrons collect just beneath that insulation and form a thin conducting path from the source to the drain.
这条通道就叫沟道。
This is called the channel.
去掉电压，电子就散开了，沟道消失，开关就关上了。
Remove the voltage and the electrons disperse, the channel disappears, and the switch turns off.
随着晶体管越做越小，源极和漏极离得太近，即使开关应该关着，电流也能从沟道漏过去。
As transistors shrank, the source and the drain got so close together that current could flow through the channel even when the switch was supposed to be off.
我们需要更好的办法来控制沟道，防止电流泄漏。
We needed a better way to control the channel and prevent current from leaking through.
解决办法就是让栅极从更多方向包住沟道，这样控制得更紧。
The fix was to give the gate a tighter grip on the channel by touching it from more sides.
在最初的平面晶体管中，栅极只从顶部接触通道。
In the original planar transistor, the gate only touches the channel from the top.
FinFET晶体管将通道挤压成硅的薄垂直鳍片。
The FinFET transistor squeezes the channel into a thin vertical fin of silicon.
栅极像布一样覆盖在鳍片上，从三个侧面控制通道。
The gate drapes over the fin, so it controls the channel from three sides.
接下来的进展是不仅覆盖通道的顶部和侧面，还要覆盖底部。
The next progression from there was to cover not only the top and the sides of the channel, but also the bottom.
这项技术被称为全环绕栅极，它将通道切成细条，每条都被栅极完全包裹。
This technology is called gate-all-around, and it slices the channel into thin ribbons, each of which gets completely wrapped around by the gate.
但要让全环绕栅极工作，需要新材料和新的制造步骤。
But getting gate-all-around to work required new materials and new manufacturing steps.
要构建这些悬浮的硅条，首先将它们夹在交替的临时占位材料层之间，这些材料占据栅极最终会占据的空间。
To build these floating ribbons of silicon, you first sandwich them between alternating layers of a temporary placeholder material, which holds the space where the gate will eventually go.
我们使用占位材料，因为真正的栅极材料无法承受后续的工艺，包括在约1000摄氏度的温度下烘烤晶圆。
We use a placeholder because the materials in the real gate wouldn't survive the processing that comes after, which involves baking the wafer at around 1,000 degrees Celsius.
等这些高温步骤完成后，芯片制造商就会蚀刻掉临时材料，让硅带悬空。
Once these hot steps are done, chip makers etch away the placeholder, leaving the ribbon suspended.
然后，他们在每条硅带周围的空隙里填充一层薄薄的特殊绝缘体，叫做高K材料，目的是让栅极能更强烈地控制通道。
Then they fill the gaps around every ribbon with a thin coat of a special insulator called a high-K material, whose purpose is to let the gate pull more strongly on the channel.
接着，在这层材料上面，再放上栅极本身的金属。
And then on top of this material, they put the metal of the gate itself.
FinFET在1989年就在实验室里得到了验证，而英特尔在2011年才实现大规模生产。
FinFET was demonstrated in a lab in 1989 and reached volume production at Intel in 2011.
栅极全包围晶体管在1988年，也就是早一年，就已经被验证了，但三星直到2022年才开始生产这种芯片。
A gate-all-around transistor had been demonstrated a year earlier in 1988, but Samsung didn't begin producing gate-all-around chips until 2022.
所以，FinFET和栅极全包围这两种想法，其实差不多是同一时期发展起来的，但投入生产却相差了十年。
So these ideas, FinFET and gate-all-around, were developed around the same time, but they reached production a decade apart.
我想问问克里斯，为什么这项栅极全包围技术花了这么长时间才实现。
I wanted to ask Chris why it took so long to get to this current gate-all-around technology.
那你能不能给我讲讲，从技术到大规模生产，这个过程是怎么走的？
Maybe you can walk me through, then, the process of getting into high-volume manufacturing.
我想具体了解一下，一旦你有了一个想法，比如我们要把通道做得更小，我们要把它包围起来，那么材料科学方面的其他问题，以及如何不破坏栅极，这些到底是怎么解决的？
I want to understand concretely, once you have an idea that, hey, we're going to make the channel smaller, we're going to surround it, all the other problems of material science and figuring out how to not destroy the gate, how did they actually get figured out?
为什么花了这么长时间？
Why did it take so long?
全环绕栅极就是一个很好的例子，因为早在90年代——
Gate-all-around's a good example, because back in the '90s-
……我们就知道这个想法了，但我们也知道在把它投入大规模生产时会遇到这些问题。
... we knew of this idea, but we knew there was going to be these problems on how you put this into high-volume manufacturing.
与此同时，还有其他技术，比如高K金属栅极、应变硅、鳍式场效应晶体管等等。
And at the same time, there's other things like high-K metal gate, there's strained silicon, there's FinFETs that are out there.
所以这有点像，什么时候才是解决这些问题的合适时机？
And so it's kind of like, when's the right time to go and tackle those?
嗯，你不想在不得不做之前就去碰它。
Well, you don't want to tackle something before you have to.
所以如果你有其他可以提升性能的方法，你会先去做那些。
And so if you have these other things that can drive performance, you would go and do that.
我们就是沿着这条路走过来的。
We went through this path where we did this.
我们做了应变硅、高K金属栅极，还有FinFET，然后发现，嗯，我们还需要更进一步。
We did strained silicon, high-K metal gate, we did FinFETs, and then it became, well, we need to do things further.
怎么才能做到呢？
How do we get there?
其实，全环绕栅极才是最终的晶体管形态。
Well, gate-all-around's really the ultimate transistor out there.
也许现在是时候开始解决那些问题了。
Maybe it's time to go and start tackling some of those issues that you have.
你说得对。
And you're right.
现在你得考虑怎么把高K金属栅极和全环绕栅极结合起来。
Now you have to look at how you put high-K metal gate in with gate-all-around.
所以，这种创新是需要时间的。
So it's that innovation that takes time.
有时候你需要新材料，有时候你需要不同的工具才能完成某些事情，这需要工具供应商去发明创造。
Sometimes it's you need new materials, sometimes it's you need a different tool in order to be able to do some of the things that you need to go do, and that requires invention from the tool vendors.
你得去找工具供应商说：“嘿，我需要一个能做XYZ的工具。”
You have to go to the tool vendor and say, "Hey, I need a tool that can do XYZ."
“我需要一种气体，能沉积那种特定的材料，用在那个里面。”
"I need a gas that can deposit this particular material that goes into that.
“我需要一个具有这种特性的加热吸盘。”
I need a heating chuck that has this characteristic to it."
所有这些都需要时间，而且有些是迭代的，你得跑一个全环绕栅极晶体管。
All those things take time, and some of it's iterative, where you have to run a gate-all-around transistor.
你说：“哦，这个不行。”
You say, "Oh, well, that didn't work.
“让我想想我的假设哪里出了问题，然后用不同的结构再试一次。”
Let me figure out what was wrong with my hypothesis and try it again with some different structure."
从单纯把平面晶体管越做越小、享受登纳德缩放带来的好处，到如今我们身处的这个世界，研发的本质发生了怎样的变化？
How has the nature of R&D changed from the era of just making planar transistors smaller and smaller and just getting the benefits of Dennard scaling to the world we're in today?
是不是研发过程完全不一样了？以前就是不断把东西做小、做小、再做小。
Is it just a totally different kind of R&D process where previously you were just like, let's make things smaller, smaller, smaller.
现在你得同时考虑性能的其他方方面面。
Now you have to look at all these other facets of performance at the same time.
而且尺寸上的改进也没那么容易了。
And improvements in size don't come as easily.
跟我说说，是不是从那时候起，研发过程发生了关键性的变化？
Walk me through whether there was some crucial change in the R&D process at that point.
看看八九十年代，确实主要是靠摩尔定律和光刻技术推动的。
If you look at the '80s and '90s, yes, it was driven really by Dennard scaling, lithography.
我们就是不断把东西做小。
We just make things smaller.
晶体管变得更快、更可靠，而且节奏非常可预测。
Transistors got faster, and they got more reliable, and it was very predictable cadence.
到了2000年代，我们发现光靠这个已经不够了。
When we started to hit 2000s, what we saw was that's not good enough anymore.
我们需要做一些不同的事情。
We need to do something different.
对我来说，这成了创新的黄金时代。
And to me, it became this golden age of innovation.
对于每一个技术节点，你打算如何提供更多的缩放，如何提供更高的性能？
For each technology node, how are you going to provide More scaling, how are you going to provide more performance?
于是这推动了应变硅的发展。
And so it drove things like strained silicon.
它推动了高K金属栅极。
It drove high-K metal gates.
它推动了鳍式场效应晶体管。
It drove FinFETs.
它推动了全环绕栅极。
It drove gate-all-around.
它推动了背面供电。
It drove backside power.
这些东西在八九十年代，你会觉得，'哦，不，我们可不想碰那些'，因为我们就一直沿用同样的工艺流程，然后直接缩小尺寸就行了。
These are things that in the '80s and '90s, you would be like, "Oh, no, we're not touching any of that," because we just continued to have the same process flow and we'd just scale it.
但对我来说，作为一个晶体管爱好者，这真的很棒，因为现在玩法开放了。
But that's really for somebody like me, who's a transistor junkie, it's awesome because now the playbook's open.
你可以做各种事情。
You can do all sorts of things out there.
你可以引入新材料。
You can bring in new materials.
看看我们九十年代用的材料数量和现在用的材料数量对比一下。
Just look at the number of materials we used to use in the '90s versus the materials today.
可能增加了十倍。
It's probably gone up 10X.
而且有很多创新。
And there's a lot of innovation.
比如原子层沉积。
There's atomic layer depositions.
你是在一个原子一个原子地控制这些东西。
You're controlling atom by atom, this stuff.
所以处理工艺的方式变了很多，以前是尽量什么都不改，现在就像抡起大锤把东西砸开，想出些新点子。
So it's changed a lot how you approach the process as to before it was try to not change anything, to now it's like take the sledgehammer and start just tearing the thing up and come up with some new idea.
对于14A工艺，英特尔正在使用一种新型光刻机，高数值孔径极紫外光刻机。
For 14A, Intel is using a new kind of lithography machine, High-NA EUV.
它使用和现在极紫外光刻机一样的极紫外光，但改变了光学系统。
It uses the same extreme ultraviolet light as today's EUV machines, but changes the optics.
NA，也就是数值孔径，衡量的是机器镜子能将多大角度的光锥聚焦到晶圆上。
NA, or numerical aperture, is a measure of how wide a cone of light the machine's mirrors can focus onto the wafer.
能聚焦的光锥越宽，光能刻出的点就越小。
The wider the cone you can focus, the smaller the spot that your light can carve.
标准极紫外光刻机的NA是0.33。
Standard EUV machines have an NA of 0.33.
高数值孔径把它提高到0.55。
High-NA widens it to 0.55.
所以高数值孔径光刻机一次就能印出大约1.7倍更小的特征。
So High-NA can print features about 1.7 times smaller in a single pass.
当特征比光刻机能印的还小时，芯片制造商就得把图案分成多次曝光，每次印不同的特征。
When features are smaller than the lithography machine can print, chip makers have to split the pattern across several passes, each printing a different set of features.
最密集的图案可能需要两次、三次甚至四次曝光。
The most tightly packed patterns can require two, three, or even four passes.
每多一次曝光，就会占用这台价值约两亿美元机器的宝贵时间，而且还会增加缺陷的风险。
Each additional pass takes up valuable time on a machine that costs around $200 million, and it introduces another opportunity for defects.
高数值孔径机器价格大约贵一倍，但能减少所需的曝光次数。
High-NA machines cost about twice as much, but they can reduce the number of passes that are needed.
所以，决定它们是否物有所值的关键，就在于能节省多少时间，以及能降低多少缺陷风险。
So the question which determines whether they justify their higher price is how much more time they save and how much they reduce the risk of defects.
现在你们在14A工艺上用了高数值孔径EUV设备，而台积电说对他们来说，这些设备在成本上还不划算。
Now you guys are using High-NA EUV tools for 14A, whereas TSMC has said that they don't make economical sense yet for them.
你们是怎么判断下一代光刻设备是否值得采用的呢？
How do you decide whether the next litho tool is the one that is ready to adopt or not?
High-NA就是一个很好的例子，因为我们的技术架构和台积电不同，所以面对同样的设备，我们会得出不同的结论。
And High-NA is a good example of where, because of the architecture of our technology versus TSMC's, we make different conclusions off of the same tool set.
我们用的是背面供电技术。
We use backside power.
这意味着你实际上可以放宽正面的间距要求，这样就能直接用High-NA来打印。
That means that you actually alleviate some of the pitch requirements you have on the front side, and that allows you to print that directly with High-NA.
台积电因为没有背面供电，所以必须用更紧密的间距，而High-NA做不到这一点，所以他们只能采用双重曝光EUV。
TSMC has to run very tighter pitches because they don't have backside power, and they can't do that with High-NA, so they have to use double patterning EUV.
所以对他们来说，High-NA帮助不大。
So for them, it's not very helpful.
但对我们来说，帮助很大。
For us, it is very helpful.
在14纳米节点上，我们把它作为一个选项保留下来，我们会和客户讨论，因为它有一定的价值。
Now at 14, we've left it as an option, and it's something that we'll have a discussion with the customer on because there's some value proposition of it.
不过它也会带来一些复杂性。
There's some complexity that it adds.
克里斯提到的是一种叫做背面供电的技术。
Chris is referring to a feature called backside power.
芯片有两种不同的布线。
A chip has two different kinds of wiring.
电源线负责给晶体管供电，需要做得比较粗。
Power lines deliver electricity to the transistors, and they need to be thick.
信号线让晶体管之间可以互相通信。
Signal lines let the transistors talk to each other.
信号线要细得多，而且彼此之间需要保持一定距离，避免一条线的信号干扰另一条线的信号。
They're much thinner, but they need to be spaced apart so that the signal from one wire doesn't interfere with the signal from another.
以前，所有的电源线和信号线都得挤在晶体管的上方。
In the past, all of these power lines and signal lines had to be crammed together on top of the transistors.
英特尔最新的工艺把这些电源线移到了晶体管的下方，也就是晶圆的背面。
Intel's newest process moves these power lines below the transistors to the back of the wafer.
这样上方就腾出了空间，信号线就不用排得那么密了。
This frees up space on top, so the signal lines don't have to be packed as tightly.
这个变化让High-NA对英特尔来说变得值得了。
This change makes High-NA worth it for Intel.
如果没有背面供电，布线会非常密集，即使使用High-NA也需要多次曝光才能完成。
Without backside power, the wiring is so tight that it would require multiple passes to print, even with High-NA.
有了背面供电，一次High-NA曝光就够了。
With backside power, a single High-NA pass is enough.
现在外部公司可以委托英特尔来制造他们设计的芯片了。
Outside companies can now commission Intel to manufacture chips that they've designed.
他们遵循英特尔的工艺设计套件，也就是PDK，这相当于一个菜单，列出了特定工艺能制造什么以及制造规则。
They follow Intel's process design kit, or PDK, the menu of what a given process can build and the rules for building it.
对于计划在14A上开发的客户，你们现在就需要把这一点锁定在PDK里吗？
Do you need to lock that into your PDK right now for customers who are planning on developing on 14A?
这目前是PDK中的一个选项，我们会和每个客户单独讨论，看他们是否想走这条路。
It's an option in the PDK today, and we're handling it as a customer-by-customer discussion that we have as to whether or not they want to go down that path or not.
关于18A，有公开报道说PDK存在延迟或问题，导致一些指令无法正常工作，这让人们很难使用你们的代工服务来制造芯片。
So for 18A, there was public reporting that there were delays or issues with the PDK such that some instructions didn't work, and it was difficult for people to use your foundry to build their chips.
跟我说说英特尔成为代工厂，然后拥有一个PDK，让其他客户也能用它来制造他们自己的芯片，这个过程是怎样的？
Tell me about the process of Intel becoming a foundry and then having a PDK that other customers can use to make whatever chip that they're making as well.
成为代工厂确实有一个学习曲线，我们的竞争对手也经历过这个过程。
There's definitely a learning curve to how you become a foundry, and that's something that our competitors have gone through as well.
PDK就是一个很好的例子。
PDK is a good example of that.
几十年来，我们一直是IDM，我们直接跟产品团队沟通，给他们看我们的晶体管数据，来回分享数据，并没有一个正式的PDK流程。
For decades, we've been an IDM, and we've gone to our product teams and we've shown them our transistor data, and we share that data back and forth, and we haven't had a formal PDK-type process.
所以这是我们必须在18A上实施的新流程，而18A一开始并没有PDK。
So that's a new process that we've had to go implement on 18A, and 18A started out not having a PDK.
因此，我们从客户那里收到了很多反馈，关于他们对PDK质量和成熟度的期望，以及他们希望在其中看到哪些信息。
And so there's definitely a lot of feedback we've got from the customers as to what they expect for quality and maturity of the PDK, what sort of information that they want to see in there.
所以我们努力把这些反馈融入进去，确保我们有一个满足客户需求的PDK。
And so we've tried to incorporate that into making sure that, hey, we have a PDK that meets our customers' requirements.
我觉得我们最终做到了，我们开始拥有这样的PDK，而14A从一开始就会具备这些。
And I think that's where we've ended up, is that we're starting to get PDKs that have this, and 14A will have that from the get-go.
它的PDK质量非常高。
It has very high-quality PDKs.
再说，PDK的成熟度是有指标的，比如0.5、0.9、1.0，我们一直在收集客户反馈，并把这些反馈融入到PDK的质量提升中。
Again, there's maturity metrics for what is a PDK.5 versus a .9 versus a 1.0, and we're constantly going through and taking customer feedback and incorporating that into the quality of our PDK.
在英特尔的大部分历史中，它的晶圆厂只生产英特尔的芯片。
For most of its history, Intel's fabs made only Intel's chips.
这可能就是台积电能够获得优势的部分原因。
That could be part of what allowed TSMC to gain an edge.
服务众多客户让台积电有更多的晶圆可以学习，有更多的收入可以再投资，也有更大的压力去按时完成任务。
Serving many customers gave TSMC more wafers to learn from, more revenue to reinvest, and more pressure to hit deadlines.
基本上，所有企业客户都有一系列共同的产品要求，如果你想开始和他们谈生意，就必须满足这些要求。
Basically, all enterprise customers have a shared set of product requirements that you have to meet if you want to even start talking about doing business with them.
比如单点登录，这样员工就可以用公司账户登录你的应用，还有目录同步，这样当有人离职时，他们的访问权限会自动被关闭。
These are things like SSO, so employees can log into your app with their company accounts, or directory sync, so that whenever someone leaves, their access gets shut off automatically.
这些功能比你想象的要难做对，而且自己内部开发的投入产出比并不划算。
These features are harder to get right than you think, and the risk-reward for building them in-house doesn't really make sense.
稍微好一点的单点登录可能不会加速你的增长，但一个坏掉的肯定会拖后腿。
A slightly better version of SSO probably won't accelerate your growth, but a broken one will definitely stunt it.
WorkOS 让你能用到所有常见企业功能中经过实战检验的版本。
WorkOS gives you access to battle-tested versions of all the most common enterprise features.
比如单点登录、SCIM、基于角色的访问控制、审计日志等等。
Things like SSO, SCIM, RBAC, audit logs, and more.
WorkOS 还提供专门为智能体设计的这些功能版本，让它们能登录、获取合适的权限，并在你的产品中执行操作。
WorkOS also has versions of these features that are purpose-built for agents, so they can log in, grab the right permissions, and take actions within your product.
所有这些功能只需几行代码就能接入。
All of these features can be plugged in with just a few lines of code.
所以你可以直接加上它们，然后开始向企业销售。
So you can add them and get started selling to enterprises.
OpenAI、Anthropic 和 Thinking Machines，以及超过3000家公司，都依赖 WorkOS 来满足他们的企业需求。
OpenAI, Anthropic, and Thinking Machines, as well as more than 3,000 other companies, all rely on WorkOS to meet their enterprise requirements.
如果你想加入他们，就去 workos.com，告诉他们是我推荐你来的。
If you want to join them, go to workos.com and tell them that I sent you.
如果一只蝴蝶在60年代扇动翅膀，你能想象一个世界，在那里“全环绕栅极”这个词甚至没人听说过，这个概念也没人熟悉，但人们却在思考科技树上一个完全不同的分支吗？
If a butterfly flapped its wings in the '60s, could you imagine a world where gate-all-around is not even a word people have heard of, an idea people are familiar with, but people are thinking of an extremely different branch of the tech tree?
你觉得科技树上能有多深的地方会完全不一样？
And how far down the tech tree do you think things could be totally different?
会不会我们连铜都不用了？
Could it be like we're not even using copper?
如果你看看，比如说，晶体管和互连——
If you look at, say, transistors and interconnects-
……
...
我觉得我们在晶体管和全环绕栅极上达到的成就，以及它成为我心目中理想的晶体管结构，这在某种程度上是不可避免的。
I think where we've gotten to as far as the transistor and gate-all-around and it being the ideal transistor structure that I have, I think was somewhat inevitable.
就像我说的，在90年代，我们已经在讨论这类事情了。
As I said, in the '90s, we were already talking about these type of things.
背面供电，那个倒是挺前卫的。
Backside power, that one's pretty out there.
我觉得即使在90年代，说要剥离整个硅衬底，把线路放在背面，这个想法可能有点超前。
I think even in the '90s, the idea that you're going to strip off the entire silicon substrate and put lines on the backside, that one is probably something that's a little bit out there.
铜当然是最好的导线材料，所以我不知道除了铜还能用什么别的。
Copper, of course, copper wires are the best, so I don't know how you would end up somewhere else besides copper.
我觉得那确实挺超前的。
I think that's pretty out there.
但你们正在探索这个变量。
But you guys are exploring the variable.
我认为在一些最紧密的间距上，用其他材料替代铜是不可避免的，所以这就是一个很好的例子，说明会有另一种材料介入。
I think for some of the very tightest pitches, I think it's inevitable that you will replace copper, and so that's a good example of where you will have another material that will come in there.
但对于较大的线路，我觉得铜还是主流。
But for the larger lines, I think copper is about where it's at.
我觉得一旦开始做全环绕栅极晶体管和背面供电，你就进入了一个非常不同的领域。
I think that once you start to do gate-all-around transistors and you do backside power, now you start to enter a very different regime.
因为现在你看到的不是简单的衬底上堆叠一切，而是完全不同的结构。
Because now you see it's not, hey, there's just some substrate and you stack everything on top.
现在你有一个晶体管悬浮在互连线上，你会想：“好吧，那我为什么不能有晶体管、互连线，然后再来更多的晶体管、更多的互连线呢？”
Now you've got a transistor which is floating an interconnect, and you're like, "Okay, well, why don't I have transistors, interconnect, and then more transistors, more interconnect?"
我们现在做的这种3D堆叠，只是把独立的芯片叠在一起，现在你会想：“为什么我不能直接构建一个这样的完整结构呢？”
This whole 3D stacking that we now do with just discrete chips that we stack on top of each other, now you're like, "Why can't I just build an entire structure like this?"
你在内存、NAND、DRAM上都能看到这种情况。
You see it with memory, NAND, DRAM.
它们有一些非常惊人的3D结构。
They have some incredible 3D structures.
NAND已经做到了。
NAND already does it.
DRAM也在讨论这件事。
DRAM talks about it.
但我认为DRAM最终也会走向这条路。
But I think that DRAM inevitably is going to go there, too.
所以很多人会说：“哦，不，我们不会这么做，因为嘿，我们未来五年内做不到。”
So a lot of people say, "Oh, no, we're not going to do this because, hey, we can't do it in the next five years."
哎呀，别这样，咱们把时间尺度拉大一点。
Well, come on, let's put a larger timescale on this.
放到十年、二十年的尺度。
Let's put 10 years, 20 years.
到2045年，你觉得能做到吗？
In 2045, do you think you could do it?
这时候你才会说：“哦，对，到那时候我们可能会有一些非常奇特的结构。”
And now you start to say, "Oh, yeah, I could see us having some pretty exotic structures at that point."
所以我们总是被未来四年的可能性所限制，因为就像我一直说的，当人们问“你觉得技术扩展会怎么发展？”
So we limit ourselves by what we see as possible in the next four years, because as I've always said, when people say, "Hey, how do you see technology scaling going?"
是的，我们大概能看到四年后的情况，然后到了那四年，你会说：“对，我觉得再过四年还能有新的东西。”
Yeah, we have visibility about four years, and then you get out to that four years and you go, "Yeah, I think there's something we can do another four years out of that."
然后到了那四年，你又会说：“对，我觉得还能再做点什么。”
And then you get to that four years and you're like, "Yeah, I think you can do something."
但如果你开始谈十年，那就很难说会是什么样了。
But if you start to talk about 10 years, yeah, it becomes hard to say what it's going to be.
克里斯提出的向上堆叠的想法，可以从晶体管本身开始。
Chris's idea of building upwards could start with the transistors themselves.
芯片使用两种类型的晶体管，分别叫N型和P型，它们的工作原理相同，但电荷方向相反。
Chips use two types of transistors called N type and P type, which work the same way, but with the charges reversed.
几乎每个电路都是通过把它们配对来构建的。
Nearly every circuit is built by pairing them up.
如今，芯片制造商把它们并排放在一起。
Today, chip makers build them side by side.
下一步就是直接把它们叠在一起，以节省空间。
The next step is to stack them directly on top of each other in order to save space.
原则上，这样可以在同样的面积里容纳两倍的晶体管。
In principle, that fits twice as many transistors into the same area.
这种设计叫做CFET，也就是互补场效应晶体管的缩写。
This design is called a CFET, short for complementary field-effect transistor.
但每增加一层，都会增加制造步骤和成本，还会导致热量积聚，而且没有明确的散热途径。
But every extra layer adds manufacturing steps and cost and also leads to heat building up that doesn't have a clear way to escape.
因为逻辑电路比存储消耗更多电力，所以像HBM或3D NAND那样堆叠DRAM的做法，在逻辑电路上很难实现，因为存在散热问题。
Because logic consumes more power than memory, you can't do stacks of DRAM that make HBM or 3D NAND as easily with logic because of the heat issue.
那么从长远来看，根本问题是不是就在于如何散热？
Is that the fundamental issue then over the long run, is how you both dissipate the heat?
所以有三件事你需要考虑——
So there's three things that you have-
当你试图说，嘿，是什么限制了计算能力？
... when you try to say, hey, what limits compute?
好的。
Okay.
就是你能多快完成开关操作？
It's how fast can you do the switch?
也就是设备的频率。
So the frequency of the device.
完成这个开关需要消耗多少电力？
How much power does it take in order to do that switch?
所以就是它的能效问题。
So the power efficiency of it.
第二个问题是，如何散去开关操作产生的热量。
And the second one is, how do you dissipate the heat that was generated by doing that switch?
这就是热管理方面的问题。
And that's the thermals piece of it.
我觉得热管理这部分，其实这些都不是新问题。
And I think the thermals piece is, and these are not new problems.
你可以往前看20年，就能找到关于这三点的文章。
You can go back 20 years, and you can see articles on these three things.
所以问题就是，对，热管理，你怎么处理，特别是当你开始讨论这些3D类型的器件时。
And so the question is, yeah, thermals, how do you deal with that, particularly when you start to talk about these 3D type devices?
我觉得确实需要那种系统级的分析和仿真工具。
I think that there is a need for that sort of system-level analysis and simulation tools.
我觉得我们还处于起步阶段，因为我们才刚刚开始研究这个。
I think we're at its infancy because we've just started to look at this.
但这确实是一个限制因素，而且将来也会是。
But it is a limiter and it will be a limiter.
不过，再说一次，这些问题我们是可以解决的。
But, again, these are problems that we can go solve.
问题可以通过努力来解决，但工程时间有限，实验用的晶圆也有限。
The problems respond to work, but engineering time is finite and so are the wafers for experiments.
在成千上万的问题中决定优先处理哪些，这本身就是推进一个制程节点最困难的部分之一。
Deciding where they go across thousands of problems is itself one of the hardest parts of bringing up a node.
我旁听过英特尔的一次热点议题会议，那些决策就是在那里做出的。
I sat in on one of Intel's Hot Topics meetings, where those decisions get made.
好的，我现在和凯文·费舍尔在一起，今天早上他在热点议题会议上定下了调子，你们在会上讨论了如何改进18A和18A技术。
Okay, I'm here with Kevin Fisher, who was laying down the law this morning at the Hot Topics meeting, where you guys were discussing how you're improving 18A and 18A technologies.
是的。
Yes.
然后人们会带着他们正在做的各种实验、各种提高良率和性能的想法来找你，然后你和你的整合工程师会告诉他们你需要什么数据，告诉他们应该怎么做，告诉他们你认为怎样能加快进度。
And people would come to you with these different experiments they were running, different ideas they had for improving yield and improving performance, and then you and your integration engineers would tell them what data you needed, tell them how they should proceed, tell them how you think could move things faster.
我希望大家能感受到这些会议的文化氛围。
I want people to have a sense of the culture at these meetings.
让我印象深刻的一点是，这正在成为你们最先进制程节点的瓶颈。
And so one thing that I found striking is just that this is bottlenecking your most advanced node.
你们希望进展迅速，所以采取了强硬手段。
You want progress to happen fast, and so you lay down the hammer.
我觉得普通工程师并不了解这些决策对英特尔利润和客户影响的严重性和紧迫性。
I would say the average engineer doesn't understand the stakes or the urgency of how this is going to impact Intel's bottom line, how it's going to impact our customer.
他们根本看不到这些问题。
They just have no visibility to those issues.
所以他们通常只会按照自己设定的一套标准去执行。
So they will typically have a certain set of criteria that they want to go capture.
他们会遇到这样的困境：'我提出了要求，但被拒绝了，我就到此为止。'
They'll hit boundaries of, "I asked for something and someone said no, and I'm done.
我想我得不到我要求的东西了。
I guess I can't have this thing that I asked for."
在这个行业里，你学到的第一件事就是永远不会有完整的数据。
One thing you learn in this industry is that you will never have a complete data set.
如果你非要等数据完整了再行动，那你就等太久了。
If you want to wait for a complete data set, you've waited too long.
那时候已经来不及了。
It's already too late.
所以我在那些会议上做的很多事，就是决定某个决策我们要承担多大风险，或者不冒这个险。
So a lot of what I end up doing in those meetings is I decide how much risk we're going to take on a certain decision or not take on a certain decision.
你得说：'听着，我们现在就上吗？'
And you need to say, "Look, do we go now?
我们要开始冒生产的风险吗？
Do we start risking production?"
因为你在拿底线冒险。
Because you're risking the bottom line.
你在拿收入冒险。
You're risking revenue.
我担心你会把我描绘成一个恶人，因为我对大家很严厉。
I'm worried you're going to put me in the light of being an ogre because I'm putting the hammer down on people.
有这样的名声挺好的。
That's a great reputation to have.
这确实是在传达紧迫感。
It's really conveying urgency.
对。
Yes.
每一天都很重要。
Every day counts.
你能给我讲一个可能出现的具体问题吗？
Can you walk me through a particular issue that might come up?
嗯，今天早上你看到的一个例子就是外延结节。
Well, one of the examples you saw this morning, which is epi nodules.
外延是外延生长的简称，意思是在现有材料上生长新材料。
Epi is short for epitaxy, which means growing new material on top of an existing one.
芯片制造商将气体流过加热的晶圆，气体在晶圆表面留下原子。
Chipmakers flow gases over a heated wafer, and the gases leave atoms on its surface.
底层材料的晶体结构起到模板的作用。
The crystal structure of the material underneath acts as a template.
每个新原子与下方的原子对齐，新层延续相同的晶体结构。
Each new atom lines up with the atoms below it, and the new layer continues the same crystal.
芯片制造商在制造芯片的多个阶段都会使用外延技术。
Chipmakers use epitaxy at several stages of making a chip.
在凯文描述的步骤中，他们用外延技术在栅极两侧生长出小晶体，作为源极和漏极。
In the step Kevin describes, they use it to grow the source and the drain as small crystals on either side of the gate.
所以在外延沉积过程中，会出现异常生长，就像长了个小肿瘤一样。
So during the deposition of our epitaxy, we get abnormal growth, a little thing like a tumor.
它长得特别快。
It's growing super fast.
这就会引发问题，因为一个外延层可能会错误地连接到另一个外延层，导致晶体管无法正常工作。
And that causes problems because one epi will short to the wrong epi, and you get transistors not working.
然后你得缩小范围，想想怎么解决这个问题。
And then you've got to narrow it down to how are you going to fix it.
过去十年，英特尔的芯片一直有一个叫处理器追踪的功能。
For the past decade, Intel's chips have had this feature called Processor Trace.
打开这个功能后，它会记录你的程序运行的所有代码，而且细节非常丰富，之后你可以回放，重建每一次函数调用。
When you turn it on, it starts recording all the code your program runs, and it captures enough detail that you can go back later and reconstruct every single function call.
大多数公司不需要这么详细的记录，但简街需要。
Most companies don't need that level of detail, but Jane Street does.
他们需要调查交易系统中那些转瞬即逝的瞬间，比如对网络数据包响应延迟的情况。
They need to investigate specific fleeting moments in their trading systems, things like a delayed response to a network packet.
这些事件往往太短暂，大多数调试工具都捕捉不到。
Those events tend to be too brief for most debugging tools to catch.
所以当简街的一位工程师注意到处理器追踪这个功能时，他就开始摆弄它，后来他和一位暑期实习生把这个探索变成了一个叫Magic Trace的新工具。
So when one of Jane Street's engineers noticed Processor Trace, he started playing around with it, and then he and a summer intern turned that exploration into a new tool called Magic Trace.
Magic Trace利用处理器追踪的输出，为简街提供了一份历史记录，显示在某个特定时刻之前发生的每一次函数调用。
Magic Trace leverages the output from Processor Trace to give Jane Street a history of every function call leading up to a specific moment of interest.
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这个项目完全是自下而上搞起来的。
This project was completely bottoms up.
一开始只是某个工程师觉得有价值的一个想法。
It started just as something that one engineer thought would be valuable.
现在简街的做市商和开发人员每天都在用Magic Trace。
And now traders and developers across Jane Street use Magic Trace every single day.
如果你想在一个被信任去追求自己认为最重要想法的地方工作，简街正在招聘研究员和工程师。
If you want to work somewhere where you're trusted to pursue the ideas that you think matter most, Jane Street is hiring researchers and engineers.
去janestreet.com/dwarkesh了解更多。
Go to janestreet.com/dwarkesh to learn more.
你今天早上观察到的其中一个部件是我们正在研究的一种特殊清洁方法，它可以消除结节。
One of the pieces that you observed this morning was a special clean that we were looking at, which would eliminate the nodule.
所以结节会沉积，然后我们会把它清除掉。
So the nodule would deposit, and then we'd get rid of it.
其他一些讨论则是关于结节的来源，从根源上消除结节。
Some of the other discussion was, well, the source of the nodule, get rid of the source of the nodule.
那你怎么决定——这里有个问题。
So how do you decide what-- There's some issue.
你怎么判断问题的根源是什么？
How do you decide what the source of it is?
大多数情况下，我们是高度并行工作的。
For the most part, we work highly parallel.
那你怎么决定呢？
So how do you decide?
有时候并不清楚哪个是解决问题的最简单方法，所以你会同时尝试所有可能的修复方案。
It's not always evident what the easiest way to fix the problem is, so you work on all the potential fixes.
而且有时候，最先想到的那个方案并不是最终有效的。
And sometimes it's not the one you expect first.
一旦我们确认这是技术上的一个主要问题，就会召开这个热点议题会议，通过这种方式把资源分配到各个工程团队，从而加快工作进度。
Once we've identified it as a primary problem for the technology, that's where this hot topics meeting gets involved, and that's how we align the resources into those engineering teams so that we can accelerate the work.
你提到我们有一个快速通道流程。
You said that there's some fast-track process for us.
是的。
Yes.
晶圆可以更快地通过——
Wafers can move through faster-
当然。
Sure
……如果它们在某些实验中成为瓶颈的话。
... if they're bottlenecking some experiment.
我们在工厂里有一套分级的系统，叫做“热箱”，每一级的热箱速度都会快一些，工厂就是这样优先处理特定批次，也就是在工厂里流转的那块硅片。
So we have a tiered system of what we call hot boxes in the factory, and every grade of hot box goes a little bit faster, and it's just how the factory prioritizes that particular lot, that block of silicon that's running through the factory.
我们最高等级的热箱，也就是一级热箱，在工厂里是飞速通过的。
So our highest grade of hot box, hot box one, races through the factory.
它在每一台设备上都有优先权，但这会拖累整个工厂的效率。
It gets priority at every single tool, but it's a drag on the entire factory.
如果这里有工厂的人，他们其实不喜欢动用这个特权，因为为了追求极快的速度，你会导致设备使用效率低下。
If you had a factory person in here, they don't like using, playing that card because you're ending up using the tools inefficiently so that you can go super, super fast.
你可以把它想象成一条高速公路，你专门留出一条车道给拼车车辆。
Think of it as a highway, and you set aside that one lane for the carpool.
这条车道其实谁都能用，但你说：“不行，只能拼车用。”
Which everyone could use, but you're saying, "Okay, it's just a carpool."
这就是我们的最高优先级热箱。
That's our hot box one.
所有其他车辆都从那条车道清出去，只让那个实验跑，然后那个实验就在高速公路上飞速前进。
Everyone clear out of that lane except for that one experiment, and that one experiment races down the highway.
凯文的工作就是决定现在生产线上跑什么。
Kevin's job is deciding what goes on the production line now.
但前一天，我和杰克·卡瓦拉罗斯去了英特尔的研发实验室，去看那些还没准备好进入节点的想法。
But the day before, I went to Intel's research lab with Jack Cavallaros to see ideas that aren't ready for the node yet.
我们先从布线开始。
We started with wiring.
晶体管只有和其他晶体管连接起来才有用，而在现代芯片上，这需要在晶体管上方堆叠十几层金属线，这叫做互连。
A transistor is only useful once it's connected to others, and on a modern chip, that takes more than a dozen layers of metal wires stacked above the transistors, called interconnect.
这些导线是铜做的，但随着它们越来越细，铜就开始出问题了。
These wires are made of copper, and as they shrink, copper starts to run into trouble.
英特尔正在研究一种替代材料，钌。
Intel is exploring a replacement, ruthenium.
钌的电阻率更高，那你们为什么还要研究钌作为未来的材料呢？
Ruthenium has higher resistivity, so why are you guys exploring ruthenium for the future?
有意思的是，当铜导线的尺寸不断缩小时，会遇到各种挑战。
So interestingly enough, as you scale the dimensions of those copper wires, you run into challenges.
比如，铜通常需要一层衬垫才能沉积到导线槽里。
For example, copper requires typically a liner in order to deposit the copper to fill those lines.
钌在这方面就很不一样，因为它是可以刻蚀的材料，这样一来，就不需要那层衬垫了。
Ruthenium is very different in that regard because it's a material that we can actually etch And as such, by etching it, we don't need that liner.
所以当尺寸缩到很细的时候，如果能用无衬垫替代有衬垫，钌就开始占优势了。
So now you scale those very fine dimensions, and if you can trade off that resistive liner with no liner, ruthenium starts to win.
所以存在一个临界点，在这个点上钌的导电性和电阻率会比铜好得多，这个点大约在20纳米间距的范围内，也就是说，你可以想象间距的一半是金属导线，另一半是绝缘的介质。
So there is a crossover point that ruthenium will have much better conductivity, better resistivity than copper, and that's roughly in the 20 nanometer pitch range, which means if you can imagine half of the pitch is your metal line and the other half is the dielectric that isolates.
那这个衬层是什么？
So what is the liner?
衬层你可以把它想象成一种粘合层或者过渡层，用来沉积铜并让它粘住——
The liner is, think of it almost like a glue layer or transition layer that we need in order to deposit the copper and have it stick-
——并且与下方的铜线连接起来。
... and make that connection to the copper lines below it.
这些铜线都是相互交错、彼此连接的。
These are all interlocking copper lines that interconnect to each other.
但每次沉积铜的时候，下面总是有一层衬层。
But every time you deposit copper, you've always had a liner underneath it.
在过去，这层衬层可能占据了整个导电通道的很大一部分。
And in the past, that liner may have been a significant portion of the entirety of that conduction path.
但随着时间的推移，我们不断缩小它、让它变得更薄，所以铜又重新成为有力的竞争者。
But over time, we've scaled it, made it thinner, and so copper comes back into play as a contender.
我很好奇的是，你们怎么判断一项技术已经成熟，可以投入大规模生产了？
One thing I'd be curious about to know is how you decide that a technology is mature and ready for high volume manufacturing.
所以说到10纳米，你提到你们从铜转向了钴，而且那可能带来了一些问题。
So with 10 nanometer, you're mentioning you guys moved on from copper to cobalt, and there were potential issues with that.
你们怎么判断这项技术能大规模应用呢？
How do you decide that this technology is going to work at scale?
把这些材料集成到像晶体管生态系统这样复杂的系统中，涉及很多很多不同的组件。
So the integration of these materials into such a complex system as the transistor ecosystem involves many, many different components.
可扩展性是一方面，但能否集成又是另一方面。
The scalability is one part, but its ability to integrate is another.
当时我们决定用钴的时候，它是领先的选择。
At the time we made a decision for cobalt, it was the forerunner.
那时候它的表现确实更强。
The results were stronger at the time.
但随着我们与外部生态系统合作，也就是提供这些材料和集成工具的供应商生态系统，我们后来找到了解决方案，可能会让铜重新成为两者中更强的那个。
But as we work with our ecosystem externally, the vendor ecosystem that provides these materials and the tools that we integrate them with, we find solutions down the road that may bring copper back in line as being the stronger of the two.
事实也正是如此。
And that's exactly what happens.
我们每经历一代技术，都会评估多种方案，而随着我们接近推出可量产产品的目标时间，我们必须做出决定。
Every technology that we go through, we will evaluate multiple options, and as we get closer to our time horizon for delivering a manufacturing-worthy product, we have to make a decision.
当时领先的方案是钴，现在又回到了铜，也许将来会是钌。
And the leading option at the time was cobalt, now it's copper again, and perhaps in the future, it'll be ruthenium.
我很想听听你对CFET的看法。
I'd love to get your thoughts on CFET.
基本上就是把晶体管堆叠起来——
Basically stacking-
当然可以。
Absolutely
……一个叠一个。
... the transistors on top of each other.
这方面进展如何？
What is progress like there?
你们能不断堆叠更多层吗？
Can you keep making more and more layers?
只有两层吗？
Is it just two?
能堆到三层、四层吗？
Can you go three, four?
最高能堆多少层？
How high can you get?
目前对CFET的评估正在进行中，不只是我们在做，我们的竞争对手也在做。
So that evaluation of CFET is currently underway, not just by us, by our competition.
外面的实验室也在研究这个。
Labs externally are looking at it.
这是堆叠技术的终极形态。
It is the ultimate in stackability.
我们之前不得不把晶体管越压越紧，现在某种程度上可以放松一些了，因为我们要把它们堆叠起来。
We're taking transistors that had to be compressed more and more, and we're relaxing that in some ways because we're going to stack them on top of each other.
但堆叠并不意味着它们之间没有互连。
But the act of stacking does not mean that they're not interconnected.
以前那些连接要么在顶部，要么在底部，就像你们从我们的新闻稿里看到的那样，现在必须垂直穿过晶体管之间，这是一个新的挑战，因为挖沟槽和填充沟槽的深宽比变得越来越难。
What used to be connections on the top or even on the bottom, as you've seen from our press release, now has to go vertically in between the transistors, and that's a new challenge because the aspect ratio of creating trenches and filling those trenches becomes more and more difficult.
所以这不像堆叠晶体管那么简单——
So it's not as straightforward as stacking the transistors-
……因为你还得考虑怎么把它们连接起来。
... because you still have to think about interconnecting them.
问题是不是在于蚀刻出那么深的孔？
Is the issue there the etch to get that deep hole?
蚀刻的深宽比确实是个大问题。
Aspect ratio for the etches is a big part of it.
我们正在和供应商合作，推动这方面的进展。
We're working with our vendors to evolve on that.
但关键还在于用什么填充那些极小的空间，因为填充有时候会留下气隙或者填不满的孔洞，这就不理想了。
But it's also what you fill those very tiny spaces with, because filling can sometimes leave air gaps or holes that never really fill, and that's not ideal.
我猜实验室里应该已经有一个CFET的版本在运行了。
I assume there's a version of CFET that works inside this lab.
现在正在用的晶圆或者工艺是什么样的？
What is the kind of wafer or process or whatever that is working right now?
那下一步是什么？
Then what's the next step?
下一步是什么？
What's the next step?
在完全进入大规模量产之前，下一步是什么？
What's the next step until it's inside the full high volume process?
在推进这些技术的过程中，尤其是像CFET这样复杂的架构，而不只是基础的化学或材料，我们需要开发一些短流程的测试载体，以便更快地获得反馈。
Part of the process of evolving these technologies, especially something more complex like an architecture, not just a basic chemistry or a material, but a full architecture like CFET, is that we have to make short-loop vehicles that can give us faster turnaround.
正常的制造流程可能需要一个月甚至更长时间，才能完成数千道工序。
The normal manufacturing process can take a month or longer to complete the thousands of steps that it goes through.
我们的目标是把这些流程中的单元模块拿出来，逐一进行验证。
Our goal here is to take unit cells of that process and qualify them.
所以我们利用短流程测试载体来获取电学参数和化学参数，从而解决那些挑战和瓶颈。
So we take advantage of short-loop vehicles that can give us electrical parameters, chemical parameters that can resolve some of those challenges, those speed bumps.
一旦解决了这些问题，我们就会把它们组合成一个更复杂的测试载体。
And once we've resolved them, then we combine them into a more complex test vehicle.
所以在这里你会发现的东西非常简单。
So what you would find in here is something very simple.
你可能在做一个二极管，或者一个电容器，这些是晶体管的组成部分。
You might be making a diode, you might be making a capacitor, which are components of the transistor.
随着这些组件不断演进，性能变得更强更好，你就会把它们组合起来，进入下一个阶段，也就是晶体管本身。
And as those evolve and become stronger, better performing, you combine them to make the next stage, which might be the transistor itself.
所以在CFET的例子中，你可能不会选择做四层纳米片叠在四层上面。
So in the CFET example, you might not choose to do four ribbons on top of four ribbons.
你可能只会选择做一对一，因为自然来说，处理这么高的结构，其高宽比会变得越来越有挑战性。
You might just choose to do one-on-one, because naturally, the aspect ratio of dealing with something that much taller becomes more and more challenging.
所以我们会有一个简化版的CFET，只有一根NMOS的线和一根PMOS的线，这样简化了我们的工作，但仍然帮助我们评估器件的堆叠以及它们之间的互连。
So we would have a simplified version of a CFET, which has only one wire for the NMOS and one wire for the PMOS, and that simplifies our job, but it still helps us evaluate the stacking of devices and how they will interconnect.
但是这里的特征尺寸会和最终的一样小吗？
But are the feature sizes here as small as they will be eventually?
还是说特征尺寸会更大？
Or are the feature sizes bigger?
哦，当然会。
Oh, absolutely.
在某些情况下，至少是一样小的。
In some cases, at least as small.
哦。
Oh.
比如，你听说过二维材料吧，就是那些过渡金属二硫化物。
For example, you've heard of 2D materials, these transition layer dichalcogenides, they're called.
这些材料非常非常薄。
They're very, very thin materials.
基本上就是一层原子那么厚——
They're essentially one monolayer of atoms-
……我们处理的就是这种。
... that we deal with.
这些沉积过程可以在这个实验室里完成。
Those depositions can happen in this lab.
我们可以评估这些薄膜的导电性、接触能力以及调节导电性的能力，也就是晶体管所起的作用。
We can evaluate those films in terms of conductivity, our ability to contact them, our ability to modulate that conductivity, which is what the transistor does.
所以是的，我们不仅能够沉积原子尺度大小的超薄薄膜，还能打印非常小的特征结构。
So yes, we do have the ability to not only deposit films that are very small and thin To the atomic scale, but also print very small features.
我们拥有EUV技术或电子束技术，可以打印非常小的特征，类似于我们最终在生产中会制造的那些。
We have EUV technology or E-beam technology that can allow us to print very small features, similar to what we will eventually make in production.
所以我想，由于缺乏这方面的背景，我直觉上不太理解，为什么现在就能做出这么小尺寸的CFET。
So I guess I don't understand intuitively, lacking the context in this process, why that you have the features that are as small for a working CFET right now.
是的。
Yes.
那为什么还要等十年才能用在我的手机里呢？
Why will it take 10 years for it to be in my phone?
我知道有个过程，但为什么这个过程这么长？
I understand that there's a process, but why is it such a long process?
当你面对像CFET这样的架构和一种新材料时，答案会略有不同。
The answer is slightly different when you're dealing with an architecture like CFET versus a novel material.
材料当然面临着沉积、蚀刻、去除的挑战，以及它们与上下其他层的兼容性。
Materials have, of course, the challenges of being deposited, etched, removed, their compatibility with other layers above and below.
所有这些都必须先研究清楚，然后才能投入生产线。
All those things have to be researched first before you put them in a production line.
一种架构可能看起来像是一个简单的演进。
An architecture may seem like a simple evolution.
哦，你是在把纳米带晶体管并排制造。
Oh, you're making nanoribbon transistors next to each other.
把它们堆叠起来有什么问题呢？
What's wrong with just stacking them?
但堆叠的过程当然会增加蚀刻、沉积、清洁的纵横比，而技术可能还没准备好。
But the act of stacking them, of course, increases the aspect ratio for etches, depositions, cleans, and the technology may simply not be ready yet.
但如果你已经在这里做出来了，那说明有一种版本的技术已经准备好了，对吧？
But if you've already made it here, there's a version of the technology that's ready, right?
对。
Correct.
所以我们做了一个简化版本，可能比不上我们现在平面的并排纳米带技术，但我们需要把它发展成两个纳米带，或者加入合适的金属和介电材料，才能让这个器件发挥出最大性能。
So we've made a simplified version that may not be an advantage over our current planar side-by-side technology of nanoribbons, but we need to evolve it to make it maybe two nanoribbons or to add the right type of metals and dielectrics in order to extract the maximum performance out of that device.
明白了。
Got it.
好。
Okay.
所以这就像是一个长长的尾巴——
So it's like a long tail of-
有上千个不同的步骤，所有这些步骤都必须以非常独特的方式结合在一起，才能让性能达到甚至超越之前的技术。
There's 1,000 different steps that all have to come together in a very unique way to make the performance compatible or actually supersede the prior technology.
这些想法通常是在哪里失败的？
Where do the ideas tend to fail?
所以你有20个关于二维材料的想法。
So you have 20 ideas that are 2D materials.
对。
Correct.
你是怎么判断某个想法不值得继续往下做的？
What is the kind of way in which you're like, "This is actually not worth pursuing further?"
有时候，我们会发现材料的一些基本特性，跟后续的工艺流程合不来。
Sometimes the idea becomes something that we discover fundamentals about the material that will be incompatible with the rest of the processing that we do.
最初阶段的实验可能只是简单的沉积，你会觉得，行，我能把薄膜沉积上去，能观察它，能测量它，但一旦我想给它做接触，什么都粘不上。
The first level of experiments may simply be very simple depositions and you say, "Okay, I can deposit the film, I can look at it, I can measure it," but the moment I try to make a contact to it, nothing sticks.
可能只是很基本的问题，比如下一步工艺的附着力，根本没法附着在这种材料上。
It could be something fundamental as simple as the adhesion of the next step in the process simply has no way to adhere to the material.
所以，就因为这么简单的原因，你可能就把一种材料给排除了。
So you may rule out a material because of something as simple as that.
更复杂的挑战可能是后续工艺中，材料会跟下游步骤产生气体反应。
More complex challenges might be the subsequent processing may have gaseous interactions with downstream steps.
比如说，我沉积了薄膜，用其他材料把它封住了，但封得不够严密，所以第三步、第四步或者第五步工艺可能还是会跟它发生反应，改变它的性质。
So, for example, I've deposited the film, I've capped it with other materials, but they're not hermetic, and so my third or fourth or fifth step in the process may actually still interact with it and change its properties.
这样一来它就不稳定了，我们得为那个流程找到更好的密封方法，如果找不到办法控制住，那对我们来说就是死路。
That makes it unstable, and now we have to find better hermetic sealing for that process, and if we don't find a way to control it, then it's a dead end for us.
堆叠晶体管目前还停留在研究实验室阶段。
Stacking transistors is still in the research lab.
而堆叠整个芯片已经投入生产了，它解决的是另一个问题，也就是不同芯片之间如何通信。
Stacking whole chips is already in production, and it tackles a different problem, how separate chips communicate with each other.
现代计算机被分成多个部分，每个部分都针对不同的任务进行了优化。
Modern computers are divided into multiple parts, each optimized for a different task.
比如，英伟达的Blackwell数据中心GPU把两个巨大的处理器芯片拼在一起，周围还堆了八层高带宽内存。
For example, NVIDIA's Blackwell data center GPU joins two huge processor chips and surrounds them with eight stacks of high-bandwidth memory.
这些芯片之间需要不断来回传输数据，在AI领域，往往不是原始计算速度，而是数据传输的速度限制了整个工作负载完成的速度。
These chips have to constantly send data back and forth with each other, and in AI, the speed of that traffic, not the raw computation itself, is often what limits how fast the workload finishes.
想象一下两个芯片并排放置，通过它们相对的边缘进行通信。
Imagine two chips side by side, communicating through their facing edges.
如果你把每个芯片的宽度和长度都翻倍，那么电路面积会变成四倍，但用于连接的边缘长度只增加两倍。
If you double each chip's width and length, you'd have four times the area for circuitry but only twice the edge length for connections.
这就是面积和周长的问题。
This is the area versus perimeter problem.
随着晶体管越来越密集，芯片的计算能力增长得比数据传输能力快。
As transistors become denser, a chip's ability to do computations increases faster than its ability to move data around.
业界多年来一直知道这个问题，所以发明了多种技术来解决它。
The industry has known about this problem for years, so multiple technologies have been invented to address it.
完成的电路必须经过最后两道工序：键合和封装。
The completed circuits must undergo two last operations, bonding and packaging.
芯片制造完成后，还需要与其他芯片以及计算机的其他部分连接。
Once a chip is made, it still has to be connected to other chips and to the rest of the computer.
这一步叫做封装，在过去几十年里发生了很大的变化。
That step is called packaging, and it has changed a lot in the last few decades.
从宏观上看，你可以这样理解封装的演变。
At a high level, you can think of the evolution of packaging like this.
最初，芯片是并排排列的。
Initially, chips were laid out side by side.
连接它们的导线从一颗芯片的侧面延伸到另一颗芯片。
Wires connecting them went out the side of one chip to another.
为了提高通信密度，业界引入了一块共享的硅片，叫做中介层，让多颗芯片可以放在上面。
To allow for more communication density, the industry introduced a shared piece of silicon, called an interposer, for multiple chips to sit on.
芯片可以通过直接穿过中介层的布线与其他芯片通信。
A chip can talk to other chips through the wiring that runs directly through the interposer.
这种封装方式通常被称为2.5D。
This type of packaging is often called 2.5D.
另一种提高连接密度的方法是将芯片直接键合在一起。
Another way to increase connection density is to bond chips directly to one another.
这样可以缩短芯片之间的连接，但早期版本使用焊料凸点，这些凸点体积大且会增加电阻。
This allows for shorter connections between chips, but the early versions of this idea use solder bumps, which are bulky and increase resistance.
更好的做法是跳过焊料，直接将两颗芯片的信号线连接融合在一起。
It would be better to skip the solder and fuse the signal wire connections of the two chips directly to each other.
这被称为混合键合，是半导体行业目前最重点投资的技术之一。
This is called hybrid bonding, and it is one of the technologies the semiconductor industry is investing in the most.
混合键合的原理是将一个芯片的铜互连与另一个芯片的铜互连对齐。
Hybrid bonding works by aligning the copper interconnects of one chip with those of another.
然后，将这些芯片压在一起并加热，使它们的互连膨胀，从而弥合芯片之间的间隙。
Then these chips are pushed together and heated so their interconnects expand and bridge the gap between the chips.
这个过程也会让铜周围的绝缘表面粘合在一起。
This process makes the insulating surfaces around the copper bond as well.
因此，通过去掉焊料凸点，你最终能得到更密集的连接。
And so by removing the solder bumps, you end up with much denser connections.
但这项技术直到现在才进入量产，是因为它需要时间来克服对齐和缺陷方面的挑战。
But the reason this technology is only now entering volume manufacturing is because it took a while to iron out the alignment and defect challenges that it introduced.
在封装实验室里，我问了英特尔先进封装技术开发部门的总监泰勒·奥斯本，他们是如何将这项技术付诸实践的。
In the packaging lab, I asked Tyler Osborne, a director in Intel's Advanced Packaging Technology Development group, how they put this into practice.
英特尔花了50多年时间优化其CPU的速度，但其中许多优化，比如缓存、分支预测和推测执行，都降低了可预测性。
Intel has spent over 50 years optimizing its CPUs for speed, but lots of these optimizations, like caching and branch prediction and speculative execution, reduce predictability.
完全相同的指令，执行一次可能需要4个周期，而下次可能需要300个周期。
The exact same instructions can take four cycles to execute one time and 300 the next.
当你把数十亿条指令堆在一起，并在多个线程和核心上执行时，这些不确定性会累积成各种难以复现的bug。
When you stack billions of instructions together and execute them across multiple threads and cores, these non-determinisms compound into all sorts of hard-to-reproduce bugs.
如果你做的是严肃的系统，你肯定遇到过这种情况。
If you work on serious systems, you've definitely experienced this.
Antithesis解决这个问题的方法有点疯狂。
Antithesis solved this by doing something a bit crazy.
他们造了一台100%确定性的计算机。
They built a 100% deterministic computer.
他们找出了Intel x86架构中所有可能引入不确定性的入口。
They identified every single door in Intel's x86 architecture where non-determinism could leak in.
网络数据包、磁盘读取、温度传感器，甚至时间本身。
Network packets, disk reads, temperature sensors, even time itself.
他们要么把这些入口全部封死，要么用受控的模拟来替代。
And they either welded each of these shut or slotted in a controlled simulation.
这台确定性计算机只是一个基础。
This deterministic computer is just a foundation.
在此基础上，Antithesis 构建了一个测试平台，能把多年的生产环境加固压缩到几分钟内完成，让你的软件在数千个并行世界中运行，注入故障并智能引导每个世界走向十亿分之一概率的失败，这种失败你自己根本没法测试出来。
On top of it, Antithesis built a testing platform that compresses years of production hardening into minutes and runs your software through thousands of parallel worlds, injecting faults and intelligently steering each one towards a one-in-a-billion failure that you'd never be able to test yourself.
正是这种确定性，支撑了我前几期节目里提到的 Antithesis 所有那些不可思议的功能。
This determinism is what's behind all the other insane Antithesis features that I've mentioned over the past few episodes.
它让你能复现任何 bug，还能在测试运行中时间旅行到任意一点。
It's what lets you reproduce any bug and time travel to any point in a test run.
最重要的是，它让你或你的智能体能把每次失败都追溯到根本原因。
Most importantly, it's what lets you or your agents trace every failure back to its root cause.
去 antithesis.com/dwarkesh 了解更多。
Go to antithesis.com/dwarkesh to learn more.
混合键合有两种不同的方式：一种是芯片对芯片，另一种是芯片对晶圆。
Two different ways you could do hybrid bonding is die to die and then die to wafer.
也许你可以谈谈这两种方式的各自优势，以及哪种在实际应用中效果更好。
And maybe you can talk about the advantages of both and which one actually practically works better.
当然可以。
Sure.
实际上在英特尔，通常，我想你提到的die to die，我们一般叫wafer to wafer。
So actually around Intel, typically, I think as you're referring to die to die, we typically call it wafer to wafer.
我们实际上是把一整片晶圆和另一片晶圆粘合在一起。
So we actually take a full wafer and another wafer and bond them together.
这种方法在CMOS图像传感器行业现在非常流行，实际上基本主导了那个行业。
That's an approach that's really popular right now in the CMOS image sensor industry, and in fact, basically dominates it.
而且它也在被考虑用于其他领域，比如内存堆叠，人们发表过各种相关的想法。
And it's being looked at for other things like memory stacking, all kinds of stuff people have published ideas about.
不过，这种方法的一个挑战是，你需要晶圆上的芯片完美匹配，并且左右对称。
One of the challenges with that, though, is that you need dies that perfectly match each other and are perfectly left-handed and right-handed.
所以你必须能够精确地将一个芯片与另一个芯片粘合。
So you have to be able to bond exactly one to the other.
所以芯片尺寸的一对一匹配是个挑战。
So one-to-one die size is a challenge.
如果上下两层的芯片设计不完全相同，那就有问题了。
So if they're not the exact same design device on top and bottom, that's a problem.
所以晶圆对晶圆，要确保晶圆在分类上匹配得很好，这本身就很有挑战性。
So wafer to wafer, it's just challenging to make sure that you have wafers that match really well in terms of the sort.
这边的良品阵列和那边的良品阵列。
So sort good array here versus sort good array here.
如果它们完全匹配，好芯片和坏芯片都一一对应——
If they match exactly, good die and bad die, that they all match-
……
...
那样我就能让好芯片的这项操作达到100%的良率，但这种可能性非常低。
I can get 100% yield of that operation of the good dies, but the chances of that are very low.
总会有一些随机分布，不管随机结果如何，都会导致好芯片和坏芯片的错误键合，造成损失。
It's going to be some randomization of the two, and whatever that randomization is, it's just going to be loss of good bonding to bad.
而芯片对晶圆，我就可以掌控条件。
Whereas at chip to wafer, I can dictate the terms.
我可以先切割，在芯片层面测试出已知的好芯片，然后只把已知的好芯片和已知的好芯片键合——
I can singulate and have known good dies that I've tested at the chip level and then only bond known good to a known good-
……基础位置。
... base position.
那你觉得未来做混合键合，芯片对晶圆会是主流方式吗？
Do you think then chip to wafer is the way that you'll do hybrid bonding in the future?
我觉得两种都会做。
I think we're going to do both.
我们确实两种都有能力做。
We definitely have the capability to do both.
这主要取决于客户和架构需求，不过在逻辑芯片对逻辑芯片的领域，芯片对晶圆确实很有意义。
It's really customer and architecture-driven, but certainly chip to wafer in the logic-to-logic space makes a lot of sense.
你刚才在解释，从……
So you were explaining that going-
好的。
Sure
……从先进封装到混合键合，间距尺寸在缩小。
... from advanced packaging to hybrid bonding, the size of the pitches is decreasing.
那还能再缩小多少？
How much further could that go?
这个问题问得好。
That's a wonderful question.
从历史上看，就像我们刚才说的，15年前，第一层互连的间距是130到150微米。
So historically, like we were saying, 15 years ago, first level interconnect was 130, 150 micrometer pitch.
现在在HVM中，我们在Foveros上做的是25微米的间距。
Today in HVM, we're doing 25 micrometer pitch in Foveros.
这里我们做的是10微米以下的，但已经有文献报道了。
Here we're doing sub-10, but there's already been literature out there.
实际上，每年最大的封装会议是五月份举办的IEEE ECTC会议，今年有一篇论文展示了0.45微米间距混合键合器件的可靠性数据。
In fact, the biggest conference every year in packaging is the IEEE ECTC conference that happens in May, and there was a paper there this year showing reliability data on a 0.45-micron pitch hybrid bonded device.
所以你可以想象，这比我们现在的HVI又高了一个数量级的密度。
So you can imagine that's a whole another order of magnitude and density, again, from where we are right now on HVI-
而且这种可扩展性已经得到了验证。
... and scalability that's already been proven.
所以我觉得这条路还很长。
So I see a long runway there.
在单个晶圆内部，互连之间的间距通常有多大？
Within interconnect, within a single wafer, how far separated are they usually?
在晶圆厂的后端，你可以想象，封装下面的那几层通常尺寸在一微米到半微米之间。
So, the back end of the fab, you can imagine like the few layers below packaging are typically around one micron to a half micron in size.
所以如果你能把封装尺寸降到0.5微米或更小，你几乎可以想象把芯片顶部的层去掉，然后直接连接到硅片内部更低的层，再连接到另一个更低的层。
So if you can push packaging down to 0.5 microns or below, you can almost think about taking layers off the top of the die and connecting to a lower layer within the silicon to another lower layer within the silicon.
这正是混合键合的魅力所在。
That's really where the beauty of hybrid bonding happens.
你可以想象，有一天甚至可以在两侧都减少互连层，然后键合在一起，这样两个晶体管层之间的总IR压降会更小。
You could think someday about even having reduced interconnect layers on both sides that we can bond together and have less total IR drop between the two transistor layers.
想想一旦进入那个领域，这能发展到什么程度，真的很令人兴奋。
It's really cool to think about where that could go once we get into those regimes.
其实我很好奇，对于AI来说，混合键合之所以这么强大，是因为它能带来更高的内存带宽，这很合理。
Actually, I am very curious about, for AI, it makes sense why hybrid bonding is so powerful because then you can get higher bandwidth of the memory.
当然。
Absolutely.
但你说到散热这些问题，那对于非AI应用来说，混合键合的优势又在哪里呢？
But you're saying with the issues with heat and everything, what is the advantage for non-AI applications of hybrid bonding?
问得好。
Ah, excellent question.
其实现在就有一些公司在探索非AI领域的应用，甚至包括消费级设备。
So there are companies out there that are looking at it for non-AI applications, even, in fact, in client devices.
我觉得其中一个很大的好处，首先当然是同样的互连密度，特别是在CPU和GPU之间。
And one of the big things I think that that can help with there is, well, number one, obviously the same raw interconnect density, especially between something like a CPU and a GPU.
另一个就是功耗。
But the other one is around power.
就像我们之前聊到的，互连越精细，每个比特传输消耗的能量就越少，单位是皮焦耳。
So like we talked about before, as you get to finer and finer interconnects, you can reduce the total power consumption in picojoules per bit for that interface.
所以在这些应用里，混合键合可以看作是封装技术降低整个系统功耗的另一种方式。
So with hybrid bonding in those applications, you could think about that as another way that packaging can help reduce the total system power budget.
有意思。
Interesting.
这样一来，好处就多了。
So then that gives you lots of benefits.
功耗更低，发热更少，但电气性能上的收益是一样的。
Lower power, less heat, for the same benefit in terms of actual electrical performance.
到目前为止，我们聊的都是怎么把芯片做得更好。
So far, this has been about making better chips.
问题的另一半是，如果AI实验室愿意花大价钱买更多的芯片，整个行业能造出多少来。
The other half of the question is how many chips the industry can make if AI labs are willing to pay for far more of them.
我有机会和英特尔的首席技术官Pushkar Randade聊聊。
I'm getting a chance to talk to Pushkar Randade, who is the CTO of Intel.
我很想了解，整个行业都得依赖同样的供应商，这会在多大程度上限制你们提高产能。
I'm very interested in understanding how the fact that the entire industry has to rely on the same suppliers bottlenecks your ability to ramp up production.
就拿EUV光刻机来说，ASML一年产量不到100台。
So for this EUV tool, ASML produces less than 100 of them a year.
是的。
Yes.
而且他们不打算每年生产超过100台，即使到本十年末也是——
And they don't plan to produce more than 100 a year, even by the end of the decade or-
对。
Yes
……每年也就比100台多一点点。
... significantly more than 100 a year.
这些设备要分给你们、台积电，还有所有正在扩产的内存厂商，比如SK海力士。
And that is be split between you, between TSMC, between all the memory makers who are ramping up production like SK Hynix.
是的。
Yes.
那这怎么限制你们扩大产能来满足所有这些需求呢？
How does that limit your ability to scale up to all this demand?
这确实是个瓶颈。
It is a limiter.
所以我们得充分利用现有的产能，尽量提高现有设备的生产效率。
So we have to make the most of the capacity that we already have installed, and we'll try to increase the output from our existing fleet of tools.
而且EUV或ASML并不是唯一的瓶颈。
And EUV or ASML is not the only bottleneck.
它确实比其他一些设备更紧张，但很大程度上，我们看到所有设备都面临严重的供应短缺。
It is definitely a bigger bottleneck than some of the other- Tools, but to a large extent, we're seeing all equipment seeing tremendous supply shortage.
即使其他设备有多家供应商，一旦你锁定了一个工艺流程——
Even though there are multiple providers of other tools, once you lock into a process flow-
比如18A。
... let's say 18A.
18A现在是个成熟的工艺，所以我们需要特定的设备。
18A is a mature process now, so we need a specific tool.
我们不能随便换一台不同的设备来做同样的事——
We can't just go and get a different tool for the same-
——同样的事。
... for the same.
所以，我们就被锁定在那一种工具、那一个供应商上，只能依赖它。
So therefore, we are locked into that one tool, one supplier, and so we rely on that.
这对14A有什么启示？到2028年，世界会变得那么疯狂，你打算怎么应对？
What lessons does this give for 14A in terms of by 2028, it's going to be such a crazy world?
是的。
Yes.
你如何安排，才能在产能爬坡时保持灵活性？
How do you structure things in such a way that you have flexibility in ramping?
对。
Yes.
实际上，做法是这样的——我们一直在这么做，大家一般也都这么做——就是尽量在不同节点之间保持工具的可互换性。
Actually, the way to do it, and we've been doing it, and generally everybody does it, is you try to maintain as much fungibility as possible going from one node to the next node.
比如说从18A到14A，可能80%的设备可以复用。
So let's say going from 18A to 14A, maybe you would say 80% of the toolset can be reused.
当然，14A因为几何尺寸更小，需要一些新的能力，所以也会需要一些独特的工具。
And then, of course, 14A, for example, would require some new capabilities because it's a denser geometry, so it would require some unique tools.
你有没有想过，就算你们决定投入无限的资金，每个月最多能生产多少晶圆？
Do you have a sense of what is the ultimate bottleneck of how many wafers you guys could produce a month, even if you were to decide to invest infinity money-
……用于资本支出？
... into doing CapEx?
在现有条件下，假设我们必须在给定的工具规模内最大化产出，我觉得提升空间是渐进的，因为现在的工艺良率已经很高了。
Given the existing constraints, let's say we had to maximize the output from a given footprint of tools, then I think it's incremental because the process today is already yielding pretty high.
如果良率已经很高了，每提高1%都极其困难，因为工艺已经调得很精细了。
And if your yield is already pretty high, to get every 1% extra yield is extremely hard because it's already a finely tuned process.
世界上有没有足够的工具，让你们在最先进的制程上把晶圆产量提高十倍？
Are there enough tools in the world such that you could 10X the amount of wafers you're producing at the leading edge?
十倍不行，但大概两倍是可以的。
Not 10X, but probably like 2X, yes.
这很有意思，因为AI行业十年来计算能力一直在翻三倍——
That's quite interesting because the AI industry for a decade has been 3X-ing compute-
是的
Yes
年复一年。
... year over year.
是的。
Yes.
你是说这种情况不可能持续下去。
And you're saying that that just can't continue.
除非整个供应链，从设备供应商开始，再到他们的供应商，再到他们的次级供应商，除非所有人都增加产量——
Unless the entire supply chain, starting from the equipment suppliers, their suppliers, their sub-suppliers, unless everybody produces more-
否则整体产量就无法提升。
... you can't increase the output collectively.
为了让听众了解一下AI需求有多大——
Just to give the audience a sense of how big the AI demand is-
以及它如何很好地变现你们生产的产品——
... and how well it monetizes the products you guys are producing-
你可以算一下这笔账，数字似乎表明，英特尔那边只要投入几十亿美元的资本开支，就能生产出足够的芯片或逻辑芯片——
... you can crunch the numbers, and the numbers seem to suggest that just a couple billion dollars of CapEx on Intel's account results in enough chips or the logic for enough chips-
……
...
就能为那些AI模型公司带来，比如说，一千亿美元的收入。
to produce, say, $100 billion of revenue for the AI model companies.
当然，在这个产业链里还有很多其他的参与者。
And of course, there are so many other players within that stack.
还有内存——
There's also memory-
……以及其他一些东西。
... and other things.
但想想看，仅仅几十亿美元的资本支出，而且这些支出还可以分摊到很多年——
But it's crazy that within a couple of billion dollars of CapEx, which can be amortized over many different years-
对
Yes
——每年就能产生一千亿美元的收入。
... produces $100 billion of revenue every single year.
对。
Yes.
这似乎表明，在某个时候，这种收益应该会向下渗透，而且应该会有一些——在某个时候，AI实验室可以直接说，'好吧，你们尽量多生产。'
Which seems to suggest that at some point, that should percolate down, and there should be some-- At some point, the AI labs could just say, "Well, produce as much as you can.
我们保证未来的——
We'll just guarantee future-
对
Yes
——收入流之类的。
... streams and stuff."
已经有早期迹象表明，这种情况可能已经在发生了。
There are early signs that that could actually be happening already.
需求信号实在太强了。
The demand signals are just so high.
但我觉得你刚才提到的是，价值正在技术栈的顶端积累。
But I think you were alluding to how the value is accumulating at the top of the technology stack.
基本上，我们是从三四十年前，甚至更早的完全垂直整合的行业，转向了一个非常水平化的行业，现在有晶圆厂、设备制造商，还有他们的供应商。
Which is essentially what is happening is we moved from a fully vertically integrated industry, like 30, 40 years ago, maybe longer, to a very horizontal industry, where you have foundries, you have equipment makers, you have their suppliers.
现在想想看，每个超大规模云服务商都在设计自己的芯片。
And today, you think about it, every hyperscaler is designing their own chips.
而且这些超大规模云服务商的规模非常大，比如一些模型公司，他们的需求也非常高。
And the scale of the hyperscalers is so large and some of the model companies, for example, and their demand is so high.
对，他们自己就能轻松消耗掉一整座晶圆厂的硅片产量，甚至好几座晶圆厂的。
Yeah, they could easily just consume an entire fab's worth of silicon on their own, or multiple fabs-
是的
Yes
他们自己就能消耗掉好几座晶圆厂的硅片产量。
... worth of silicon on their own.
而且他们绝对有资金来支持这一点。
And they definitely have the capital to fund that.
所以从某种意义上说，我们又在从一个水平化的世界，转向一个伪垂直整合的世界。
So in some sense, we are moving from a sort of a horizontal world again to a pseudo-
啊
Ah
……垂直整合的世界，虽然不是那种铁板一块的垂直整合，但可以说是虚拟的垂直整合。
... vertical world where it's not monolithically vertically integrated, but it's kind of virtually vertically integrated.
有意思。
Interesting.
这个行业的规模经济本质是什么？
What is the nature of economies of scale in this business?
你看台积电和英特尔在先进制程上出货的晶圆数量。
Where you look at how many wafers at the leading edge TSMC versus Intel are shipping.
台积电是英特尔的3倍以上。
Upwards of 3X for TSMC.
到了这个阶段，规模经济能带来哪些优势？
What kinds of advantages do you get at this point from economies of scale?
还是说，一旦达到某个临界点，规模经济的效应就会减弱？
Or is it that once you reach a certain point, the economies of scale get weaker?
这个问题非常重要。
That's a very important question.
整个行业完全依赖规模和规模经济。
This entire business just relies on scale and economies of scale.
如果你看看所有先进的制造公司，可能半导体代工厂的规模经济是最纯粹的。
If you look at sort of all the advanced manufacturing companies out there, probably semiconductor foundries, the scale economics is probably the purest.
原因就是固定成本高得惊人，一旦建好一个晶圆厂，大约80%的成本结构都是固定的。
And the reason for that is the fixed cost is just so incredibly high that once you build a fab, like 80% of your cost structure is fixed.
这意味着每多一个百分点的利用率，都会带来更多的收入。
And so what that means is every extra percentage of utilization is adding far more in revenue.
所以，这一点极其重要。
So therefore, it's extremely important.
我们会争取每一个额外的晶圆厂利用率百分点，同时也会争取每一个额外的晶圆厂产出百分点，比如我今天生产一些晶圆，良率是60%。
And we'll fight for every extra percent of fab utilization, but also every extra percentage of fab output, as in, let's say I'm making some wafers today and the yield is like 60%.
但如果我改进工艺，芯片良率提高到65%或70%，这可不是线性的优势。
But if I improve the process and the die yield becomes 65% or 70%, it's not a linear advantage.
就像在同样的面积下，我得到了更多的产出。
It's like I'm getting way more output for the given footprint.
所以规模经济总有提升的空间。
So there's always room to improve the economies of scale.
这也是为什么这个行业会出现这么多整合的原因之一。
And that's one of the reasons why you're seeing so much consolidation in this business.
正因为这个原因，先进制程节点上只剩下三家代工厂了。
There's only three foundries left at the advanced node for that exact reason.
而且在这个过程中，很多公司干脆就停止制造了。
And just along the way Many companies just stop manufacturing.
不知道你有没有见过一张图表，40年前有20家代工厂，随着时间推移，代工厂的数量不断减少，到现在只剩下三家了。
I don't know if you've seen, there's a chart where 40 years ago, there were 20 foundries, and over time, the number of foundries kept diminishing until today there's only three.
那么，具体来说，追上台积电的切实计划是什么呢？
What is basically then the concrete master plan to catch up to TSMC?
尽管台积电领先——
Even though TSMC is ahead-
是的
Yes
……他们在最先进制程上的需求溢出太多了——
... there's so much overflow demand at their leading edge-
完全正确
Absolutely
……现在N3工艺主要是AI加速器，可能大部分是英伟达的——
... where N3 is now majority AI accelerators, and maybe majority NVIDIA alone-
对
Yes
……所有这些对CPU和其他东西的需求，顺便说一句，这些也是AI需要的。
... that all this demand for CPUs, for other things, which are also, by the way, needed for AI.
是的。
Yes.
这股巨大的CPU需求涌入就是因为AI。
This humongous influx in demand for CPU is because of AI.
是的。
Yes.
你怎么看现在的这个机会？英特尔比台积电早几年，而台积电现在产能严重过剩。
How do you see this opportunity right now where Intel's a few years before, while TSMC is just way oversaturated?
追赶上台积电可能有多方面——
Catching up to TSMC maybe has multiple-
……多个方面。
... facets.
我觉得我们需要追赶的是规模。
I would say the catch-up that we need to do is in scale.
就像你说的，他们现在的晶圆制造规模比我们大得多，甚至比三星还大。
Like you said, they're just a much larger wafer manufacturer today than we are, and even bigger than what Samsung is.
在规模上追赶会是一个缓慢而渐进的过程。
Catching up in scale will be a slow process and a gradual process.
如果你说的是技术上的追赶，我觉得我们已经做到了。
If you meant catch up in terms of just the technology, I think we're already there.
我们可能在性能、功耗或面积密度上差几个百分点，但那种比较哪家代工厂领先或落后的说法，只有在落后或领先整整一代或两代的时候才有意义。
We may be a few percent off on performance or power, or area density, but this sort of benchmarking of one foundry is ahead or one foundry is behind, it makes sense when you're a whole generation behind or two generations behind or ahead.
那时候才会在芯片产量、芯片面积或功耗等功能上产生实质性的差异。
That's when it makes a meaningful difference in your die output or your die area or functionality like power.
但如果只差几个百分点，那其实就是在吹毛求疵了，因为现在的情况已经不能只看单一维度了。
But if you're within a few percent, you're splitting hairs at that point in time because it's not very unidimensional at this point.
不只是密度的问题。
It's not just about density.
也不只是原始性能的问题。
It's not just about raw performance.
不同的应用需要不同的侧重点。
Different applications require different vectors.
所以你可以差几个百分点，但你必须按时交付。
So you can be off by a few percent, but you need to be on time.
你的执行力必须保证良率很高，才能支持非常大规模和非常快速的产能爬坡。
Your execution needs to be such that your yields are very high to support very large and very rapid ramps.
所以实际上，这比在性能或面积上追赶几个百分点更重要。
So that actually is more important than catching up on a few percent in performance or area.
我在看一些半导体分析数据，似乎表明在晶体管密度方面——
I was looking at some semi-analysis numbers that seem to suggest that in terms of transistor density-
是的
Yes
……2028年推出的14A，能和N2相提并论吗？
... 14A, which will come out in 2028, would it be comparable to N2?
首先，我对你的基准测试有异议。
First of all, I would dispute your benchmarking.
但就像我说的，我认为大致在合理范围内很重要。
But like I said, I think it's important to be generally in the right ballpark.
要非常可预测，而且，这也不是单一维度的，我们不是只制造一种晶体管，比如14A或18A。
Be very predictable, and also, it's not unidimensional in terms of we don't build one type of transistor, let's say 14A or 18A.
我们会制造几种不同类型的晶体管。
You build a few different types of transistors.
比如说，有低漏电的晶体管，也有高性能、高驱动电流的晶体管。
Let's say there's a low-leakage transistor, there's a high-performance, high-drive current transistor.
你们在制造SRAM。
You're building SRAMs.
有高密度的SRAM。
There's a high-density SRAM.
还有高性能的SRAM。
There's a high-performance SRAM.
还有很多其他功能，比如一些模拟电路、射频电路。
There's many other functionalities like some analog circuits, RF circuits.
所以，是所有这些加在一起，才让一项技术具有竞争力。
So it's the sum of all of those that makes a technology competitive.
我觉得这让你们现在做的资本支出变得更加重要了。
I guess that makes the CapEx you do right now even more important.
现在，台积电的资本支出有望达到500亿美元。
So right now, TSMC is on track to do 50 billion in CapEx.
是的。
Yes.
今年资本支出大约500亿美元。
Around 50 billion in CapEx this year.
是的。
Yes.
你正在按计划完成大约200亿美元。
You're on track to do around 20 billion.
是的。
Yes.
但是如果你现在买的设备将决定谁能满足所有这些疯狂的AI需求——
But if the tools you're buying right now will determine who can service all this crazy AI demand-
是的
Yes
——即将到来的需求——
... that's coming up-
对
Yes
这让资本开支的差距变得更加重要了
... it makes the difference in CapEx even more important-
对
Yes
对美国和其他国家来说都是如此
... for US versus other countries.
是的，非常对
Yes, very much.
现在拿我们和台积电比有点不太公平，因为他们现在基本上给所有人做代工，而我们主要是给英特尔做代工
It's a little bit of an unfair comparison between us and TSMC today, just because today they're a foundry for basically everybody, and we're largely a foundry for Intel.
我们以后也会给别人做代工，所以到时候我们的资本开支也会增长
We'll become a foundry for others, so in due course, our CapEx will also grow.
英特尔在60年代末是从DRAM业务起家的，你们当时也生产DRAM，后来卖掉了
Intel started as a DRAM business in the late '60s, and then you guys are producing DRAM, which you sold off.
几年前，你们把闪存业务卖掉了。
A couple of years ago, you sold off your flash business.
是的。
Yes.
对，你怎么看这件事？
Yeah, thoughts on that?
给观众解释一下背景，这些现在都是数万亿美元的行业了。
For context for the audience, these are now multi-trillion-dollar industries-
是的。
Yes
因为它们在AI需求的推动下爆发式增长了。
... because they've just exploded as a result of-
是的。
Yes
AI对它们的需求。
... AI demand for them.
是的。
Yes.
显然，事后看来，卖掉闪存业务可能不是最明智的时机。
Clearly, in hindsight, probably not the smartest time to sell off a flash memory business.
当时我们这么做是有充分理由的。
There were good reasons why we did that when we did.
显然，没人能预见到如此巨大的需求。
Clearly, nobody could see this enormous demand.
但现在，基本上，世界会消耗掉所有能生产出来的计算资源，也会消耗掉所有能生产出来的存储资源。
But no, today, essentially, the world will eat up as much compute as can possibly be made, and it'll eat up as much memory as can possibly be made.
我认为，目前存储领域的供应紧张比计算领域更严重。
I would argue that the supply crunch is larger for memory today than it is for compute.
那么，我能总结一下我从你的话中得到的要点吗？
So can I summarize what it seems to me the takeaways from your-
好的。
Yes
……预测是这样的，你可以告诉我这样理解对不对？
... projections are, and you can tell me if that's correct?
对。
Yes.
边际产量实际上可以增长得非常快——
Marginal production can increase actually very fast-
是的
Yes
……大概在12个月的时间尺度上。
... on the scale of 12 months.
但到本十年末，增长的量是极其有限的。
But the amount of increase up till the end of the decade is extremely limited.
对。
Yes.
明年的产量可能会比人们预测的更高，但2030年的产量不会比人们预测的高出太多。
Production could be higher next year than what people are forecasting, but production in 2030 is not going to be significantly higher than what people are forecasting.
除非整个供应链非常快速地提升产量。
Unless the entire supply chain ramps up production very quickly.
我们现在已经是26年年中了，所以距离这个十年结束也没几年了，而且考虑到交付周期，比如说你今天下了个大订单买工具，大概要18个月才能拿到这些工具。
We're already in the middle of '26, so there's only not that many years until the end of the decade, and given the lead times, let's say you place an enormous order for tools today, and you're looking at, let's say, 18 months to get those tools.
那基本上就已经到28年了。
You're already into basically '28.
而且从那时候开始，如果你还要建新的厂房、建新的晶圆厂，基本上就要等到这个十年结束了。
And from that point on, if you have to build a new shell, build a new fab, you're basically looking at the end of the decade.
我觉得聊聊你们和Elon在Terafab上的合作会很有意思。
I think it'll be interesting to discuss the partnership you guys have with Elon on Terafab.
那边进展怎么样？
What's going on there?
嗯，Elon公开说过他想建一个晶圆厂。
Well, so Elon's publicly talked about his desire to build a fab.
我们要么建Terafab，要么就没有芯片，而我们又需要芯片，所以我们必须建Terafab。
We either build the Terafab or we don't have the chips, and we need the chips, so we're going to build the Terafab.
差不多也是这个思路。
Sort of the same thinking.
我觉得他看到了对硅、算力和内存的巨大需求增长。
I think he's seeing just an enormous increase in demand for silicon, for compute, and for memory.
而且我觉得他得出的结论是，他自己的业务会需要大量的硅。
And I think he came to the conclusion that his own businesses are going to require a lot of silicon.
所以他想，也许他应该自己全包了。
And so he thought maybe he should just do it all on his own.
不像造车，比如，这个过程非常精细复杂。
Unlike building a car, for example, this is such an intricate and complicated process.
我们觉得可以合作，帮他加快建厂的速度。
We thought we could work together to help accelerate his bringing up his fab.
但因为工具层面的瓶颈——
But because of the bottleneck at the tool level-
对。
Yes
……看起来全球硅的总量并不会增加。
... it seems like the net amount of silicon in the world won't increase.
只是如果有人要新建晶圆厂，他们能获得有保障的供应，而如果使用别人的代工厂，就未必能这样。
It's just that maybe if somebody were to start a new fab, they would get access to guaranteed supply in a way that they wouldn't have if they're working with another person's foundry.
其实不只是设备的问题。
It's actually not just tools.
晶圆厂确实需要大量的电力、水和耗材。
A fab does require a lot of power, a lot of water, a lot of consumables.
还有很多其他的投入要素。
There's many other input variables as well.
但这些是可以扩展的，而设备不行。
But those can be scaled in the way that tools cannot.
有些方面可以，但确实如此。
Some more than others, but yes.
不过，从某种意义上说，我们确实需要更多设备，但这也是事实。
But yes, in one sense, yes, we need a lot more equipment, but it is true.
我们还需要更多的晶圆厂空间，更多的洁净室容量。
We also need a lot more just raw fab space, raw clean room capacity.
所以如果你想想像英特尔这样的代工厂，它必须建造这些昂贵的设施，购买昂贵的工具——
So if you think of a foundry like Intel, which has to build these expensive facilities, buy expensive tools-
……
...
我想知道你觉得这从根本上经济上会是什么样子，能不能变得更经济，能不能更快地扩展。
I wonder what you think the economics of that fundamentally could look like, whether it could get more economical, whether it could scale faster.
就像我之前说的，这是一个资本极其密集的行业，如果你只是画一下建一个晶圆厂要花多少钱，在过去，我不知道，20年、30年、40年里，我觉得每四到五年就翻一番。
Like I described earlier, this is an extremely capital-heavy business, and if you just plot how much does it cost to build a fab, and if you just over the last, I don't know, 20, 30, 40 years, I think it's doubling every four to five years.
即使在晶圆厂内部，如果你看看光刻的成本，这是最昂贵的模块，只是图案化，它本身的翻倍速度比这个还快。
Even inside the fab, if you look at the cost to do lithography, which is the most expensive module, just patterning, that itself is doubling at more than that rate.
所以今天，一台高数值孔径的EUV扫描仪及其所有相关设备要4亿美元。
So today, a High-NA EUV scanner and all its associated equipment is $400 million.
那这意味着什么呢？
And so what does that mean?
如果这个速度继续下去，你直接画条线说：“好，那是不是意味着四年后，图案化的成本会达到8000亿美元？”
If that rate were to continue, if you just draw the line and say, "Okay, does that mean four years from now, cost of patterning is going to be $800 billion?"
8000万美元，这不太合理。
$800 million, it doesn't really make sense.
我觉得一个很有意思的思维实验是，想想有没有一些我们现在能做的、非常颠覆性的事情，而20年前我们可能做不到？
I think that a very interesting thought exercise to do is to say are there things that could be just very radically different that we could do today that we perhaps couldn't do 20 years ago?
这是一个非常规避风险的行业，而且有充分的理由，正是因为这个原因。
This is a very risk-averse industry for very good reason, for exactly that reason.
你投入了几百亿美元，真的不想冒任何风险。
You put in tens of billions of dollars, and you really don't want to take any risks.
所以你想继续按照几十年来一直的方式做事。
So you want to keep doing things the way they've been done for literally decades.
这不仅适用于半导体，实际上适用于所有行业。
And this is not just true of semiconductors, but everything, really.
但如果你几十年如一日地这样做，你就会变得墨守成规。
But if you've just kept on doing that for decade upon decade, you just become indoctrinated.
而且英特尔可能有一些新来的工程师，他们刚进来，就被教导说：‘这就是晶圆厂，这就是工艺流程。’
And there are engineers who probably work at Intel who are new, who just come in, and they're taught, "This is how the fab, this is the process flow."
他们就把这些当作金科玉律。
And they just take that as gospel.
这就是做事情的方式。
That's just how it is done.
但今天这真的是制造芯片的最佳方式吗？
But is that really the best way to build a chip today?
这确实是个值得思考的问题。
It's a really valid question.
我很想知道你暗示的是什么，因为可能是任何事情，从我们可以想办法减少光刻次数，节省这个……
I'm very curious what you're hinting at because it could be anything from we can figure out ways in which we use fewer litho passes and economize on this-
……昂贵的部件，到也许我们需要重新思考晶体管。
... expensive component to maybe we need to rethink the transistor.
那是什么层面的……
What is the level of-
我觉得以上所有方面都有可能。
I think all of the above.
好的。
Okay.
晶体管架构的演进，比如硅晶体管已经持续发展了三四十年，未来还会继续。
Transistor architecture and evolving, just a silicon transistor has continued to evolve over 30, 40 years, and that will continue.
所以你已经看到了从平面晶体管到鳍式场效应晶体管，再到现在的全环绕栅极晶体管的演变。
So you've seen the evolution from the planar transistor to FinFETs to now gate-all-around transistors.
这个路线图是存在的，而且定义得很清楚，有很多人在研究。
That roadmap exists, and it's pretty well-defined, a lot of people working on it.
但也有一些问题，比如今天真的需要无尘室吗？
But there's things like do you really need a clean room today?
基础设施真的需要像现在这样精密、复杂吗？
Do you need the infrastructure to be as sophisticated, as complex as it is today?
当然，你可以做个实验，在研究用的晶圆厂里让人吃汉堡、抽雪茄，看看良率会变成什么样。
Well, surely one can run an experiment where people are eating hamburgers and smoking cigars in the research fab and see what happens to yield.
那会是个很棒的实验，但像英特尔、台积电或三星这样的现有巨头，没人会愿意主动去做。
That would be a great experiment to run, but no incumbent like Intel or TSMC or Samsung, nobody would want to just willingly do that.
所以这就是我真正想表达的意思。
So that's what I meant really by this.
这个行业非常规避风险，这是有充分理由的。
It's a very risk-averse business for good reason.
每损失一天的生产力，我不知道要损失多少美元。
Every one day lost in productivity is I don't know how many dollars.
但未来不用建无尘室，能省下很多钱。
But you save so much money in not having to build clean rooms in the future.
但真正的问题是对未知的恐惧。
But it's really the fear of the unknown.
所以没人会愿意主动冒这个险。
So nobody is going to willingly take that risk.
但这就是为什么我觉得有时候从头开始、重新思考一切是好的，就像，好吧。
But that's why I think sometimes it's good to just start with a clean slate and rethink everything, and it's like, okay.
顺便说一句，芯片设计也是一样的道理。
Same thing applies to chip design, by the way.
我们做CPU设计的很多方法，可能都是30年前定下来的。
Many of the ways we do CPU design were probably locked in 30 years ago.
那是不是意味着现在还按老办法做就是明智的呢？
Does that mean it's smart to still do it the same way?
很可能不是。
Probably not.
但这个问题非常复杂。
But this is a very complex problem.
芯片设计比较容易——我觉得承担风险的能力可能更高，但这个（指制造）就不一样了。
Chip design is easy to-- I guess the capacity to take risk is maybe higher, this one less so.
但考虑到今天的经济状况，我觉得这个问题问得很有道理。
But given where the economics is today, I think it's a very valid question to ask.
也许有更聪明的做法。
Maybe there's a smarter way to do this.
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